wip: update yosys4gal
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@ -4,16 +4,67 @@ description: Bringing modern synthesis to 30-year old technology with Yosys and
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date: 2024-06-14
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---
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# A History Lesson
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## A History Lesson
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During the semiconductor revolution, a dilemma appeared: Designing new ICs required a lot of time and effort to create the mask,
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and iteration was expensive. At the time, IC designs were very simple, since the available tools/compute to do tasks like optimization
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or place-and-route were limited. And what if you wanted a low-volume design?
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or place-and-route were limited. And what if you wanted a low-volume design? Programmable Logic Arrays (PLAs) were an early
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approach to these problems. The idea was simple: create a flexible logic archiecture that could be modified later in the process
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to implement various digital designs. These worked by using matricies of wires in a Sum-of-Products architecture. Inputs
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would be fed with their normal and inverted forms to a bank of AND gates, which would select various inputs
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using a fuse tie on the die and create product terms. The outputs of the AND gates would then be fed into OR gates, which would
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create the sum term for the whole output.
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To address these concerns, the PAL was born. The principle was straightforward - we use Sum-of-Product notation and place a 2D grid of wires
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as a matrix interconnect. By placing tap points at the intersections of the horizontal and vertical wires, we tie them together.
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This design was popular, since it allowed for less-certain aspects of the chip to be moved to a later design process.
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Eventually, hardware people got jealous of the fast (for the time) compile-evaluate loops in software, and so PAL (Programmable
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Array Logic) was invented. These are similar to PLA logic, but the fuses are programmed using a simple programmer rather
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than a complex die process. This means that a developer with a pile of chips can program one, test it, make some adjustments,
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and then program the next. Later versions would solve the whole one-time-programmable aspect using UV-erasable EEPROM.
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{% image "./pla_logic2.svg", "Hi" %}
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Demands would increase futher and flip-flops would be added, as well as feedback capability. This allows for very complex
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functions to be implemented, since you can chain "rows" of the output blocks.
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hi
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## Back To Today: GALs in the 21st Century
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These days, modern FPGA technology can be yours for a couple of bucks. Open-source toolchains allow fast, easy development,
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and the glut of Verilog resources online makes it easier than ever to enter the world of hardware design.
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But there are times when GALs might still be useful. For one, they start up instantly. Some FPGAs have a very fast one-time-
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programmable internal ROM, but this is obviously not without drawback since the design can no longer change. In most
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cases the bitstream must be loaded from an external SPI flash. This can take a few seconds, which may not be acceptable if
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the logic is critical. Another important factor is the DIP package that is offered. This makes GALs perfect for breadboard
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applications. You could use it like an 8-in-1 74-series logic chip, changing the function depending on what you need.
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Finally, operating at 5 volts is useful when interfacing with older systems.
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But programming GALs is an excersize in frustration. Take a look at a basic combinitoral assembly file:
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```PALASM
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GAL16V8
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CombTest
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Clock I0 I1 I2 I3 I4 I5 NC NC GND
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/OE O0 O1 O2 O3 O4 I6 NC NC VCC
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O0 = I0 * I1
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O1 = I2 + I3 + I6
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O2 = I4 * /I5 + /I4 * I5
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O3 = I0 * I1 * I2 * I3 * I4 * I5
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/O4 = I0 + I1 + I2 + I3 + I4 + I5
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DESCRIPTION
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Simple test of combinatorial logic.
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```
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While it's pretty intuititve what it does, it's not exactly a stellar format for writing complex logic.
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Plus, there's no way to integrate or test this (we'll get back to this). Compared to the Verilog flow,
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with simulation, testbenches, and synthesis, the raw assembly is stuck in the 80s.
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Verilog compilers for GALs *did exist*, but they ran on old-as-dirt systems, didn't have any significant optimization
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capabilities, and were almost always proprietary. What if we could make our own open-source Verilog flow for GAL chips?
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Then we could write test benches in Verilog, map complex designs onto the chip, and even integrate our designs with FPGAs later
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down the line.
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