diff --git a/content/blog/yosys4gal/yosys4gal.md b/content/blog/yosys4gal/yosys4gal.md
index c406b64..83e334a 100644
--- a/content/blog/yosys4gal/yosys4gal.md
+++ b/content/blog/yosys4gal/yosys4gal.md
@@ -4,16 +4,67 @@ description: Bringing modern synthesis to 30-year old technology with Yosys and
 date: 2024-06-14
 ---
 
-# A History Lesson
+## A History Lesson
 
 During the semiconductor revolution, a dilemma appeared: Designing new ICs required a lot of time and effort to create the mask,
 and iteration was expensive. At the time, IC designs were very simple, since the available tools/compute to do tasks like optimization
-or place-and-route were limited. And what if you wanted a low-volume design?
+or place-and-route were limited. And what if you wanted a low-volume design? Programmable Logic Arrays (PLAs) were an early
+approach to these problems. The idea was simple: create a flexible logic archiecture that could be modified later in the process
+to implement various digital designs. These worked by using matricies of wires in a Sum-of-Products architecture. Inputs
+would be fed with their normal and inverted forms to a bank of AND gates, which would select various inputs
+using a fuse tie on the die and create product terms. The outputs of the AND gates would then be fed into OR gates, which would 
+create the sum term for the whole output.
 
-To address these concerns, the PAL was born. The principle was straightforward - we use Sum-of-Product notation and place a 2D grid of wires
-as a matrix interconnect. By placing tap points at the intersections of the horizontal and vertical wires, we tie them together.
+This design was popular, since it allowed for less-certain aspects of the chip to be moved to a later design process.
+Eventually, hardware people got jealous of the fast (for the time) compile-evaluate loops in software, and so PAL (Programmable
+Array Logic) was invented. These are similar to PLA logic, but the fuses are programmed using a simple programmer rather
+than a complex die process. This means that a developer with a pile of chips can program one, test it, make some adjustments,
+and then program the next. Later versions would solve the whole one-time-programmable aspect using UV-erasable EEPROM.
 
-{% image "./pla_logic2.svg", "Hi" %}
+Demands would increase futher and flip-flops would be added, as well as feedback capability. This allows for very complex
+functions to be implemented, since you can chain "rows" of the output blocks.
 
 
-hi
+## Back To Today: GALs in the 21st Century
+
+These days, modern FPGA technology can be yours for a couple of bucks. Open-source toolchains allow fast, easy development,
+and the glut of Verilog resources online makes it easier than ever to enter the world of hardware design.
+But there are times when GALs might still be useful. For one, they start up instantly. Some FPGAs have a very fast one-time-
+programmable internal ROM, but this is obviously not without drawback since the design can no longer change. In most
+cases the bitstream must be loaded from an external SPI flash. This can take a few seconds, which may not be acceptable if
+the logic is critical. Another important factor is the DIP package that is offered. This makes GALs perfect for breadboard
+applications. You could use it like an 8-in-1 74-series logic chip, changing the function depending on what you need.
+Finally, operating at 5 volts is useful when interfacing with older systems.
+
+But programming GALs is an excersize in frustration. Take a look at a basic combinitoral assembly file:
+
+```PALASM
+GAL16V8
+CombTest
+
+Clock I0    I1    I2    I3    I4    I5    NC    NC   GND
+/OE   O0    O1    O2    O3    O4    I6    NC    NC   VCC
+
+O0 = I0 * I1
+
+O1 = I2 + I3 + I6
+
+O2 = I4 * /I5 + /I4 * I5
+
+O3 = I0 * I1 * I2 * I3 * I4 * I5
+
+/O4 = I0 + I1 + I2 + I3 + I4 + I5
+
+DESCRIPTION
+
+Simple test of combinatorial logic.
+```
+
+While it's pretty intuititve what it does, it's not exactly a stellar format for writing complex logic.
+Plus, there's no way to integrate or test this (we'll get back to this). Compared to the Verilog flow,
+with simulation, testbenches, and synthesis, the raw assembly is stuck in the 80s.
+
+Verilog compilers for GALs *did exist*, but they ran on old-as-dirt systems, didn't have any significant optimization
+capabilities, and were almost always proprietary. What if we could make our own open-source Verilog flow for GAL chips?
+Then we could write test benches in Verilog, map complex designs onto the chip, and even integrate our designs with FPGAs later
+down the line.
\ No newline at end of file