yosys4gal/testcases/adder_downto_upto.v
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2024-04-04 01:33:47 -05:00

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Verilog

module adder_downto_upto (A, B, C);
input [2:0] A;
input [0:2] B;
output [3:0] C;
assign C = A + B;
endmodule