mirror of
https://github.com/annoyatron255/yosys4gal.git
synced 2024-12-22 10:42:24 +00:00
111 lines
2.7 KiB
Tcl
Executable file
111 lines
2.7 KiB
Tcl
Executable file
#!/usr/bin/env -S yosys -c
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yosys -import
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if { $argc != 1 } {
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puts "USAGE: $argv0 -- <VERILOG FILE>"
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exit
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}
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set fbasename [file rootname [file tail [lindex $argv 0]]]
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puts $fbasename
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exec rm -rf output
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exec mkdir output
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## Read Verilog/Liberty file
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read_verilog [lindex $argv 0]
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hierarchy -auto-top
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read_verilog -lib cells_sim.v
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read_liberty -lib techmaps/gal_dff.lib
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## First pass synthesis
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tribuf
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synth
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design -save preop
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# Map IO pins (and undo port removal for the output)
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iopadmap -bits -inpad GAL_INPUT Y:A -toutpad GAL_OUTPUT E:A:Y -outpad GAL_OUTPUT A
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expose */t:GAL_OUTPUT "%x:+\[A\]" */t:GAL_OUTPUT %d
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## DFF/SOP mapping
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dfflibmap -liberty techmaps/gal_dff.lib
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# Get count of non-clock inputs and registers
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set num_inputs [regexp -inline {\d+} [tee -s result.string select -count t:GAL_INPUT]]
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set num_regs [regexp -inline {\d+} [tee -s result.string select -count t:DFF_P]]
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set num_inputs_regs [expr $num_inputs + $num_regs]
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if {$num_regs > 0} { set num_inputs_regs [expr $num_inputs_regs - 1] }
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#abc -sop -I $num_inputs_regs -P 256
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#abc -sop -I 8 -P 8
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#abc -script "+strash;,dretime;,collapse;,write_pla,test.pla" -sop
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# Force one-level SOP
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#abc -script "abc.script" -sop
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# Resynth all too big SOPs together in multi-level SOP
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#select "t:\$sop" r:DEPTH>8 %i
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#techmap -autoproc -map sop.v
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#yosys proc
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#techmap
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#select *
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abc -sop -I $num_inputs_regs -P 7
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opt
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clean -purge
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#show -width
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## Tech mapping
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# PLAs
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techmap -map techmaps/pla.v -D PLA_MAX_PRODUCTS=7
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# Sequential OLMC
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extract -constports -map extractions/ndff.v
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extract -constports -map extractions/olmc.v
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techmap -map techmaps/olmc_seq.v
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# Combinational OLMC
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iopadmap -bits -outpad GAL_COMB_OUTPUT_P A:Y */t:GAL_SOP "%x:+\[Y\]" */t:GAL_SOP %d o:* %i
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techmap -map techmaps/olmc_comb.v o:* %x o:* %d
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# Add OLMC for internal GAL_SOPs
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techmap -max_iter 1 -map techmaps/pla_olmc_int.v */t:GAL_OLMC %ci2 */t:GAL_SOP %i */t:GAL_SOP %D
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clean -purge
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## Write output files and graph
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write_verilog "output/synth_${fbasename}.v"
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write_json "output/synth_${fbasename}.json"
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write_table "output/synth_${fbasename}.txt"
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write_blif "output/synth_${fbasename}.blif"
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write_rtlil "output/synth_${fbasename}.rtlil"
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## Verify equivalence
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# Backup and make gold and gate modules
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design -stash postop
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design -copy-from preop -as gold A:top
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design -copy-from postop -as gate A:top
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# Inverse tech map into primatives
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techmap -autoproc -map cells_sim.v -autoproc
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clean -purge
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# Verify
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equiv_make gold gate equiv
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tribuf -formal equiv
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equiv_induct equiv
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equiv_status -assert equiv
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# Get LTP from inverse tech map so FF cells are recognized
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ltp -noff
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# Restore backup
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design -load postop
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## Print final stats
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show -width -signed -enum
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stat
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shell
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