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27 lines
557 B
Verilog
27 lines
557 B
Verilog
(* techmap_celltype = "GAL_SOP" *)
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module _80_GAL_SOP (A, Y);
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parameter WIDTH = 0;
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parameter DEPTH = 0;
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parameter TABLE = 0;
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input [WIDTH-1:0] A;
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output reg Y;
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generate
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if (WIDTH == 1 && DEPTH == 1 && TABLE == 01) begin
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$_NOT_ _TECHMAP_REPLACE_ (.A(A), .Y(Y));
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end else if (WIDTH == 1 && DEPTH == 1 && TABLE == 10) begin
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$_BUF_ _TECHMAP_REPLACE_ (.A(A), .Y(Y));
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end else begin // No-op
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GAL_SOP #(
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.WIDTH(WIDTH),
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.DEPTH(DEPTH),
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.TABLE(TABLE)
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) _TECHMAP_REPLACE_ (
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.A(A),
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.Y(Y)
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);
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end
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endgenerate
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endmodule
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