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21 lines
213 B
Verilog
21 lines
213 B
Verilog
module test (
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input clk,
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output reg [0:7] counter
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);
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always @ (posedge clk) begin
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counter <= counter + 1;
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end
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endmodule
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/*module test (
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input [1:0] a, b,
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output [2:0] y
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);
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assign y = a + b;
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endmodule*/
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