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39 lines
486 B
Verilog
39 lines
486 B
Verilog
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module GAL16V8_reg_tb(
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output reg clk = 0,
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output reg [7:0] in,
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output reg oe_n,
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inout wire [7:0] io
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);
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GAL16V8_reg GAL16V8_reg_inst (
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.clk(clk),
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.in(in),
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.oe_n(oe_n),
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.io(io)
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);
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always #5 clk = !clk;
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initial begin
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$dumpfile("dump.vcd");
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$dumpvars(0, GAL16V8_reg_tb);
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#3;
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in = 8'b0000_1100;
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oe_n = 0;
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#10;
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in = 8'b0000_1001;
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#10;
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in = 8'b0000_0110;
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#10;
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in = 8'b0000_0011;
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#10;
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in = 8'b0000_1100;
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#30;
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oe_n = 1;
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#10;
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$finish;
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end
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endmodule
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