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32 lines
439 B
Verilog
32 lines
439 B
Verilog
(* techmap_celltype = "GAL_OLMC" *)
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module _80_GAL_OLMC (C, E, A, Y);
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parameter REGISTERED = 0;
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parameter INVERTED = 0;
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input C, E, A;
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inout Y;
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wire int;
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generate
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GAL_OLMC #(
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.REGISTERED(REGISTERED),
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.INVERTED(INVERTED)
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) _TECHMAP_REPLACE_ (
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.C(C),
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.E(E),
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.A(int),
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.Y(Y)
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);
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GAL_SOP #(
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.WIDTH(1),
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.DEPTH(1),
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.TABLE(2'b10)
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) trivial_sop_olmc (
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.A(A),
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.Y(int),
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);
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endgenerate
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endmodule
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