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72 lines
1,008 B
Verilog
72 lines
1,008 B
Verilog
(* techmap_celltype = "GAL_COMB_OUTPUT_P" *)
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module _80_GAL_COMB_OUTPUT_P (A, Y);
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input A;
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output Y;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b0),
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.INVERTED(1'b0)
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) _TECHMAP_REPLACE_ (
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.C(1'bX),
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.E(1'b1),
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.A(A),
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.Y(Y)
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);
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endgenerate
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endmodule
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(* techmap_celltype = "$_NOT_" *)
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module _80_NOT (A, Y);
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input A;
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output Y;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b0),
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.INVERTED(1'b1)
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) _TECHMAP_REPLACE_ (
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.C(1'bX),
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.E(1'b1),
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.A(A),
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.Y(Y)
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);
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endgenerate
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endmodule
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(* techmap_celltype = "GAL_TRI" *)
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module _80_GAL_TRI (A, E, Y);
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input A, E;
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inout Y;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b0),
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.INVERTED(1'b0)
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) _TECHMAP_REPLACE_ (
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.C(1'bX),
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.E(E),
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.A(A),
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.Y(Y)
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);
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endgenerate
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endmodule
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(* techmap_celltype = "GAL_TRI_N" *)
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module _80_GAL_TRI (A, E, Y);
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input A, E;
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inout Y;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b0),
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.INVERTED(1'b1)
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) _TECHMAP_REPLACE_ (
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.C(1'bX),
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.E(E),
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.A(A),
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.Y(Y)
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);
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endgenerate
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endmodule
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