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yosys4gal/techmaps
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annoyatron255 5c998f7b65
Add techmap README
2024-05-06 01:32:33 -05:00
..
gal_dff.lib make TCL 2024-03-18 02:12:59 -05:00
olmc_comb.v Add tristates 2024-04-04 20:39:30 -05:00
olmc_seq.v Add tristates 2024-04-04 20:39:30 -05:00
one_sop.v Add tristates 2024-04-04 20:39:30 -05:00
pla.v Add OLMC on internal combinational nodes 2024-04-04 13:54:11 -05:00
pla_olmc_int.v Add OLMC on internal combinational nodes 2024-04-04 13:54:11 -05:00
README.md Add techmap README 2024-05-06 01:32:33 -05:00
trivial_1sop_olmc.v Ensure OLMC/SOP invariant with tristate 2024-05-05 00:20:18 -05:00
trivial_sop.v Some edge cases cleaned up 2024-04-04 17:16:02 -05:00
trivial_sop_olmc.v Ensure OLMC/SOP invariant with tristate 2024-05-05 00:20:18 -05:00

README.md

Techmaps

All the yosys techmapping libraries/Verilog files used for mapping to the GAL structure. See the synth_gal.tcl file for details on how they're used. A summary is below (in the order they're used):

  • pla.v splits SOPs into a chain of SOPs with a specified size
  • trivial_sop.v replaces SOPs which are just buffers/NOT gates with buffer/NOT cells
  • one_sop.v converts GAL_SOPs with only one product into GAL_1SOPs. Used on enabled (tristate) lines
  • pla_olmc_int.v adds a combinational GAL_OLMC after a GAL_SOP. Used to insert GAL_OLMC between GAL_SOPs or enable lines
  • olmc_comb.v creates GAL_OLMCs for combinational/tristate output pads
  • trivial_sop_olmc.v adds a buffer GAL_SOP before a GAL_OLMC. Used to add GAL_SOPs between directly connect GAL_OLMCs/GAL_INPUTs
  • trivial_1sop_olmc.v same as above but for enable lines