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10 lines
142 B
Verilog
10 lines
142 B
Verilog
module NDFF_P (C, D, Q);
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input C, D;
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output Q;
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wire Y;
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$_NOT_ not_inst (.A(D), .Y(Y));
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DFF_P dff_inst (.D(Y), .C(C), .Q(Q));
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endmodule
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