mirror of
https://github.com/annoyatron255/yosys4gal.git
synced 2024-12-22 18:52:23 +00:00
9 lines
85 B
Verilog
9 lines
85 B
Verilog
module nand_gate (A, B, Y);
|
|
|
|
input A, B;
|
|
output Y;
|
|
|
|
assign Y = !(A && B);
|
|
|
|
endmodule
|