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23 lines
347 B
Verilog
23 lines
347 B
Verilog
module wrapper (
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input wire clk,
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input wire [5:0] in,
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output wire [4:0] out
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);
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wire [7:0] in_int;
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wire [7:0] io_int;
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wire oe_n;
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assign oe_n = 0;
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assign in_int = {3'b0, in};
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assign out = {io_int[3], io_int[4], io_int[5], io_int[6], io_int[7]};
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GAL16V8_reg GAL16V8_reg_inst (
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.clk(clk),
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.in(in_int),
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.oe_n(oe_n),
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.io(io_int)
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);
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endmodule
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