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15 lines
151 B
Verilog
15 lines
151 B
Verilog
module reg_tristate (
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input clk,
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input a, b, c,
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output y
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);
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reg x;
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assign y = c && b ? x : 1'bz;
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always @ (posedge clk)
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x <= a && b;
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endmodule
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