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33 lines
464 B
Verilog
33 lines
464 B
Verilog
(* techmap_celltype = "GAL_SOP" *)
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module _80_GAL_SOP (A, Y);
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parameter WIDTH = 0;
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parameter DEPTH = 0;
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parameter TABLE = 0;
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input [WIDTH-1:0] A;
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output Y;
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generate
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wire internal;
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GAL_OLMC #(
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.REGISTERED(1'b0),
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.INVERTED(1'b0)
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) olmc_inst (
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.C(1'bX),
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.E(1'b1),
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.A(internal),
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.Y(Y)
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);
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GAL_SOP #(
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.WIDTH(WIDTH),
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.DEPTH(DEPTH),
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.TABLE(TABLE)
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) _TECHMAP_REPLACE_ (
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.A(A),
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.Y(internal)
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);
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endgenerate
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endmodule
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