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72 lines
1,007 B
Verilog
72 lines
1,007 B
Verilog
(* techmap_celltype = "DFF_P" *)
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module _80_DFF_P (C, D, Q);
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input C, D;
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output Q;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b1),
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.INVERTED(1'b0)
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) _TECHMAP_REPLACE_ (
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.C(C),
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.E(1'b1),
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.A(D),
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.Y(Q)
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);
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endgenerate
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endmodule
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(* techmap_celltype = "NDFF_P" *)
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module _81_NDFF_P (C, D, Q);
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input C, D;
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output Q;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b1),
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.INVERTED(1'b1)
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) _TECHMAP_REPLACE_ (
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.C(C),
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.E(1'b1),
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.A(D),
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.Y(Q)
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);
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endgenerate
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endmodule
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(* techmap_celltype = "TRI_DFF_P" *)
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module _80_TRI_DFF_P (C, E, D, Q);
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input C, E, D;
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inout Q;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b1),
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.INVERTED(1'b0)
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) _TECHMAP_REPLACE_ (
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.C(C),
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.E(E),
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.A(D),
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.Y(Q)
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);
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endgenerate
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endmodule
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(* techmap_celltype = "TRI_NDFF_P" *)
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module _81_TRI_NDFF_P (C, E, D, Q);
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input C, E, D;
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inout Q;
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generate
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GAL_OLMC #(
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.REGISTERED(1'b1),
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.INVERTED(1'b1)
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) _TECHMAP_REPLACE_ (
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.C(C),
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.E(E),
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.A(D),
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.Y(Q)
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);
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endgenerate
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endmodule
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