mirror of
https://github.com/annoyatron255/yosys4gal.git
synced 2025-01-02 15:28:24 +00:00
10 lines
142 B
Verilog
10 lines
142 B
Verilog
module NDFF_P (C, D, Q);
|
|
input C, D;
|
|
output Q;
|
|
|
|
wire Y;
|
|
|
|
$_NOT_ not_inst (.A(D), .Y(Y));
|
|
DFF_P dff_inst (.D(Y), .C(C), .Q(Q));
|
|
endmodule
|