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https://github.com/annoyatron255/yosys4gal.git
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79 lines
1.3 KiB
Verilog
79 lines
1.3 KiB
Verilog
module GAL_SOP (A, Y);
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parameter WIDTH = 0;
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parameter DEPTH = 0;
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parameter TABLE = 0;
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input [WIDTH-1:0] A;
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output reg Y;
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integer i, j;
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reg match;
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always @* begin
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Y = 0;
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for (i = 0; i < DEPTH; i=i+1) begin
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match = 1;
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for (j = 0; j < WIDTH; j=j+1) begin
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if (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;
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if (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;
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end
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if (match) Y = 1;
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end
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end
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endmodule
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module GAL_1SOP (A, Y);
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parameter WIDTH = 0;
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parameter DEPTH = 0;
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parameter TABLE = 0;
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input [WIDTH-1:0] A;
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output reg Y;
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integer i, j;
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reg match;
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always @* begin
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Y = 0;
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for (i = 0; i < DEPTH; i=i+1) begin
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match = 1;
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for (j = 0; j < WIDTH; j=j+1) begin
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if (TABLE[2*WIDTH*i + 2*j + 0] && A[j]) match = 0;
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if (TABLE[2*WIDTH*i + 2*j + 1] && !A[j]) match = 0;
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end
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if (match) Y = 1;
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end
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end
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endmodule
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module GAL_INPUT (A, Y);
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input A;
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output Y;
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assign Y = A;
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endmodule
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module GAL_OLMC (C, E, A, Y);
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parameter REGISTERED = 0;
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parameter INVERTED = 0;
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input C, E, A;
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inout Y;
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reg internal;
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assign Y = E ? internal : 1'bZ;
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generate
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if (REGISTERED == 1) begin
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always @ (posedge C) begin
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internal <= (INVERTED == 0) ? A : !A;
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end
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end else begin
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always @ (*) begin
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internal <= (INVERTED == 0) ? A : !A;
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end
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end
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endgenerate
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endmodule
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