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wip: commit before refactor of graph code

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saji 2024-05-03 11:14:32 -05:00
parent 8bfcd28e0d
commit bb48e10488
2 changed files with 22 additions and 16 deletions
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3
compiler/src/fitter.rs
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@ -171,7 +171,7 @@ pub fn graph_convert(graph: &Graph, pcf: PcfFile, chip: Chip) -> anyhow::Result<
.iter() .iter()
.enumerate() // get the index .enumerate() // get the index
.filter_map(|(i, x)| if x.is_none() { Some(i) } else { None }) // find the ones that are .filter_map(|(i, x)| if x.is_none() { Some(i) } else { None }) // find the ones that are
.map(|i| (i, chip.num_rows_for_olmc(i))) .map(|i| (i, chip.num_rows_for_olmc(i))) // get the size of the row
.collect(); .collect();
// find the smallest row that fits. // find the smallest row that fits.
@ -185,6 +185,7 @@ pub fn graph_convert(graph: &Graph, pcf: PcfFile, chip: Chip) -> anyhow::Result<
} }
// at this point, we have mapped every OLMC. // at this point, we have mapped every OLMC.
// now use the blueprint to set the settings.
Ok(bp) Ok(bp)
} }

35
compiler/src/yosys_parser.rs
View file

@ -303,21 +303,6 @@ impl Node {
* internally. So get_outputs returns values on input_cells, since those are driven already. * internally. So get_outputs returns values on input_cells, since those are driven already.
* Likewise we reverse this for get_inputs, since the chip's outputs are our inputs. * Likewise we reverse this for get_inputs, since the chip's outputs are our inputs.
*/ */
// fn get_outputs(&self) -> Vec<Net> {
// match self {
// Self::Input(i) => i.connections.output.to_vec(),
// Self::Sop(s) => s.connections.output.to_vec(),
// Self::Olmc(o) => o.connections.get("Y").expect("Y outpu").to_vec(),
// }
// }
// fn get_inputs(&self) -> Vec<Net> {
// match self {
// Self::Input(gi) => gi.connections.input.to_vec(),
// Self::Sop(gs) => gs.connections.inputs.to_vec(),
// Self::Olmc(go) => go.connections.input.to_vec(),
// }
// }
// Returns the hashmap of String (connection name) to a list of nets. // Returns the hashmap of String (connection name) to a list of nets.
pub fn get_connections(&self) -> HashMap<String, Vec<Net>> { pub fn get_connections(&self) -> HashMap<String, Vec<Net>> {
match self { match self {
@ -531,6 +516,26 @@ impl From<YosysDoc> for Graph {
} }
} }
pub enum CellType {
Input,
Sop,
OLMC,
}
type Connections = HashMap<String, Vec<Net>>;
type Parameters = HashMap<String, String>;
pub trait Cell {
fn name(&self) -> &str;
fn connections(&self) -> &Connections;
fn params(&self) -> &Parameters;
fn ctype(&self) -> CellType;
fn nets(&self) -> Vec<Net>;
fn uses_net(&self, net: Net) -> bool;
fn net_on_port(&self, net: Net) -> Option<String>;
}
/* /*
* This graph is too general as it stands. we cannot map individual input pins * This graph is too general as it stands. we cannot map individual input pins
* like we can with our output pins. Also, i have no way of finding a specific * like we can with our output pins. Also, i have no way of finding a specific