From 8c1fd24ad6354f01fcbbcaf2d727174cece009aa Mon Sep 17 00:00:00 2001 From: annoyatron255 Date: Mon, 6 May 2024 01:42:29 -0500 Subject: [PATCH] Add extraction README/update techmap README --- extractions/README.md | 11 +++++++++++ techmaps/README.md | 4 ++++ 2 files changed, 15 insertions(+) create mode 100644 extractions/README.md diff --git a/extractions/README.md b/extractions/README.md new file mode 100644 index 0000000..addf544 --- /dev/null +++ b/extractions/README.md @@ -0,0 +1,11 @@ +Extractions +=========== + +All the yosys extraction pass Verilog file used for mapping to the GAL +structure. See the `synth_gal.tcl` file for details on how they're used. A +summary is below (in the order they're used): + +- `ndff.v` merges NOT gates and DFFs into a single cell. Used to set the active + high/low state of the GAL_OLMCs later +- `tristate.v` merges tristate cells and NOT gates or tristate cells and DFFs. + Used to combine tristate functionality into the GAL_OLMCs later diff --git a/techmaps/README.md b/techmaps/README.md index fb076f4..62c2de8 100644 --- a/techmaps/README.md +++ b/techmaps/README.md @@ -5,9 +5,13 @@ All the yosys techmapping libraries/Verilog files used for mapping to the GAL structure. See the `synth_gal.tcl` file for details on how they're used. A summary is below (in the order they're used): +- `gal_dff.lib` Liberty library for supported FFs (only positive edge-triggered + DFFs). Used to prevent yosys from using fancy flip-flops - `pla.v` splits SOPs into a chain of SOPs with a specified size - `trivial_sop.v` replaces SOPs which are just buffers/NOT gates with buffer/NOT cells +- `olmc_seq.v` converts all existing sequential elements into GAL_OLMCs this + includes special merged types from other techmap passes/extractions - `one_sop.v` converts GAL_SOPs with only one product into GAL_1SOPs. Used on enabled (tristate) lines - `pla_olmc_int.v` adds a combinational GAL_OLMC after a GAL_SOP. Used to