From 22f1a2a26b46ba60d834c8c0abff6dd74aacb9cd Mon Sep 17 00:00:00 2001 From: saji Date: Sat, 4 May 2024 16:55:22 -0500 Subject: [PATCH] fix pin ordering in SOP stuff --- compiler/src/fitter.rs | 3 ++- testcases/and_gate_reg.v | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/compiler/src/fitter.rs b/compiler/src/fitter.rs index 3145ab8..0dfc48c 100644 --- a/compiler/src/fitter.rs +++ b/compiler/src/fitter.rs @@ -162,7 +162,8 @@ fn make_term_from_sop(graph: &Graph, sop: GalSop, pcf: &PcfFile) -> Term { let product_size = sop.parameters.width; let chunksize = product_size * 2; // 00 for dontcare, 01 for negation, 10 for positive i think - let input_nets = sop.connections.get("A").unwrap(); + let mut input_nets = sop.connections.get("A").unwrap().clone(); + input_nets.reverse(); // the order is backwards from how we read it in the alg. let terms: Vec> = table .chunks(chunksize as usize) diff --git a/testcases/and_gate_reg.v b/testcases/and_gate_reg.v index 4aef88a..24c24d2 100644 --- a/testcases/and_gate_reg.v +++ b/testcases/and_gate_reg.v @@ -1,7 +1,8 @@ module and_gate (clk, A, B, Y); input A, B; -output Y; +input clk; +output reg Y; always @(posedge clk) begin Y <= A && B;