From 7aa12417e604d8a8b3955c4cc01ea4fcc9bb309d Mon Sep 17 00:00:00 2001 From: Asherah Connor Date: Thu, 27 Jun 2024 19:12:24 +0300 Subject: [PATCH] cxxrtl: opt also optimises the design with Yosys. This has a significant result on sim speed. --- niar/cxxrtl.py | 33 ++++++++++++++++++++++++++++----- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/niar/cxxrtl.py b/niar/cxxrtl.py index c3e3cfd..39352f7 100644 --- a/niar/cxxrtl.py +++ b/niar/cxxrtl.py @@ -105,24 +105,45 @@ def main(np: Project, args): cr = CommandRunner(force=args.force) with logtime(logging.DEBUG, "elaboration"): - il_path = np.path.build(f"{np.name}.il") + il_path = np.path.build(f"{np.name}.cc.il") rtlil_text = rtlil.convert(design, name=np.name, platform=platform) with open(il_path, "w") as f: f.write(rtlil_text) cxxrtl_cc_path = np.path.build(f"{np.name}.cc") - yosys_script_path = _make_absolute(np.path.build(f"{np.name}-cxxrtl.ys")) + yosys_script_path = _make_absolute(np.path.build(f"{np.name}.cc.ys")) black_boxes = {} with open(yosys_script_path, "w") as f: for box_source in black_boxes.values(): f.write(f"read_rtlil <