generated from saji/ecp5-template
138 lines
2.9 KiB
Systemverilog
138 lines
2.9 KiB
Systemverilog
module coordinator (
|
|
input clk,
|
|
output display_clk,
|
|
output out_enable,
|
|
output latch,
|
|
output [2:0] panel_rgb0,
|
|
output [2:0] panel_rgb1,
|
|
output reg [4:0] display_addr
|
|
);
|
|
|
|
reg [11:0] frame_counter;
|
|
|
|
// pixgen signals
|
|
reg pixgen_start;
|
|
reg [8:0] x;
|
|
reg [8:0] y;
|
|
wire [23:0] pix_rgb0;
|
|
wire [23:0] pix_rgb1;
|
|
wire [1:0] pix_done;
|
|
|
|
pixgen pix0 (
|
|
.clk(clk),
|
|
.start(pixgen_start),
|
|
.x(x),
|
|
.y(y),
|
|
.rgb(pix_rgb0),
|
|
.done(pix_done[0]),
|
|
.frame(frame_counter[11:4])
|
|
);
|
|
pixgen pix1 (
|
|
.clk(clk),
|
|
.start(pixgen_start),
|
|
.x(x),
|
|
.y(y + 9'd32),
|
|
.rgb(pix_rgb1),
|
|
.done(pix_done[1]),
|
|
.frame(frame_counter[11:4])
|
|
);
|
|
|
|
|
|
|
|
// bram signals
|
|
|
|
wire [35:0] din;
|
|
wire [35:0] dout;
|
|
wire [8:0] addr_r;
|
|
wire read_clk;
|
|
wire write_clk;
|
|
|
|
lineram bram (
|
|
.write_clk(clk),
|
|
.read_clk(clk),
|
|
.addr_w(bitplane_addr),
|
|
.din({3'b000, bitplane_data}),
|
|
.write_en(bitplane_wren),
|
|
.addr_r(addr_r),
|
|
.dout(dout)
|
|
);
|
|
|
|
// driver
|
|
reg write_line;
|
|
wire line_done;
|
|
|
|
hub75e driver (
|
|
.clk(clk),
|
|
.write_trig(write_line),
|
|
.panel_rgb0(panel_rgb0),
|
|
.panel_rgb1(panel_rgb1),
|
|
.display_clk(display_clk),
|
|
.out_enable(out_enable),
|
|
.latch(latch),
|
|
.done(line_done),
|
|
.pixbuf_addr(addr_r),
|
|
.pixbuf_data(dout)
|
|
);
|
|
|
|
|
|
reg [4:0] state = 0;
|
|
|
|
localparam unsigned StateInit = 0;
|
|
localparam unsigned StateStartFrame = 1;
|
|
localparam unsigned StateGenerateLine = 2;
|
|
localparam unsigned StateShowLine = 3;
|
|
localparam unsigned StateIncrementLine = 4;
|
|
// we're gonna try this
|
|
assign bitslice_start = pix_done[0] & pix_done[1]; // bitslice start when both pix done.
|
|
|
|
always @(posedge clk) begin
|
|
case (state)
|
|
StateInit: begin
|
|
x <= 0;
|
|
y <= 0;
|
|
display_addr <= 0;
|
|
write_line <= 0;
|
|
state <= StateStartFrame;
|
|
end
|
|
StateStartFrame: begin
|
|
pixgen_start <= 1;
|
|
state <= StateGenerateLine;
|
|
end
|
|
StateGenerateLine: begin
|
|
// generate data, move it into the bram.
|
|
pixgen_start <= 0;
|
|
if (bitplane_done) begin
|
|
if (x < 128) begin
|
|
x <= x + 1;
|
|
pixgen_start <= 1;
|
|
// generate next
|
|
end else begin
|
|
write_line <= 1;
|
|
state <= StateShowLine;
|
|
end
|
|
end
|
|
end
|
|
StateShowLine: begin
|
|
write_line <= 0;
|
|
if (line_done) begin
|
|
state <= StateIncrementLine;
|
|
end
|
|
end
|
|
StateIncrementLine: begin
|
|
x <= 0;
|
|
display_addr <= display_addr + 1;
|
|
y <= y + 1;
|
|
if (display_addr == 31) begin
|
|
state <= StateInit;
|
|
end else begin
|
|
frame_counter <= frame_counter + 1;
|
|
state <= StateStartFrame;
|
|
end
|
|
end
|
|
default: state <= StateInit;
|
|
endcase
|
|
end
|
|
|
|
|
|
endmodule
|