generated from saji/ecp5-template
78 lines
1.4 KiB
Systemverilog
78 lines
1.4 KiB
Systemverilog
`timescale 1ns / 100ps // 1 ns time unit, 100 ps resolution
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module hub75e_tb;
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reg clk;
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reg write_trig;
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wire [4:0] addr_out;
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wire [2:0] rgb0;
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wire [2:0] rgb1;
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wire display_clk;
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wire out_enable;
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wire latch;
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wire done;
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// block ram inputs
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reg [35:0] bram_data_in;
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reg [8:0] bram_addr_w;
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reg bram_write_en;
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wire [8:0] bram_addr_r;
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wire [35:0] bram_data_out;
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lineram bram (
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.din(bram_data_in),
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.addr_w(bram_addr_w),
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.dout(bram_data_out),
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.addr_r(bram_addr_r),
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.write_en(bram_write_en),
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.read_clk(clk),
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.write_clk(clk)
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);
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hub75e dut (
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.clk(clk),
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.write_trig(write_trig),
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.addr(addr_out),
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.panel_rgb0(rgb0),
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.panel_rgb1(rgb1),
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.display_clk(display_clk),
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.out_enable(out_enable),
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.latch(latch),
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.done(done),
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.pixbuf_addr(bram_addr_r),
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.pixbuf_data(bram_data_out)
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);
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always #5 clk = !clk;
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initial begin
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$dumpfile("wave.vcd");
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$dumpvars(0, hub75e_tb);
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clk <= 0;
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bram_addr_w <= 0;
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bram_write_en <= 1;
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repeat (1) @(posedge clk);
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for (int i=0; i < 128; i=i+1) begin
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bram_data_in <= $urandom % 'hFFFFFF;
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bram_addr_w <= i;
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repeat (1) @(posedge clk);
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end
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bram_write_en <= 1;
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write_trig <= 1;
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repeat (2) @(posedge clk);
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write_trig <= 0;
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@(done);
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repeat (20) @(posedge clk);
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$finish();
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end
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initial begin
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repeat (100000) @(posedge clk);
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$finish();
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end
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endmodule
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