generated from saji/ecp5-template
26 lines
498 B
Systemverilog
26 lines
498 B
Systemverilog
module pixgen #(
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parameter integer X_DEPTH = 9,
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parameter integer Y_DEPTH = 9,
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parameter integer RGB_DEPTH = 24
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) (
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input clk,
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input start,
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input [X_DEPTH-1:0] x,
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input [Y_DEPTH-1:0] y,
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input [7:0] frame,
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output reg [RGB_DEPTH-1:0] rgb,
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output reg done
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);
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// given x and y inputs, create an rgb output
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always @(posedge clk) begin
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if (start) begin
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done <= 1;
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rgb <= { x[6:0], 1'b0, frame, y[5:0], 2'b0};
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end
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else done <= 0;
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end
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endmodule
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