groovylight/verilog
saji d465fccaed wip: refactor and fix rightmost pixel bug
hack but now row1 doesn't work.
2024-05-22 22:26:33 -05:00
..
tb wip: 4x clock double-read bram 2024-05-09 17:31:15 -05:00
bitslicer.sv coordinator works now 2024-05-01 16:14:32 -05:00
coordinator.sv wip: 4x clock double-read bram 2024-05-09 17:31:15 -05:00
hub75e.sv wip: refactor and fix rightmost pixel bug 2024-05-22 22:26:33 -05:00
lineram.v add basic verilator sim 2024-05-19 00:15:53 -05:00
pixgen.sv fix bit-loading latency using comb logic 2024-05-02 20:30:51 -05:00