generated from saji/ecp5-template
141 lines
4.1 KiB
Systemverilog
141 lines
4.1 KiB
Systemverilog
module hub75e (
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input clk,
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input write_trig,
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output reg [2:0] panel_rgb0,
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output reg [2:0] panel_rgb1,
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output reg display_clk = 0,
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output reg out_enable = 1,
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output reg latch = 0,
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output reg done = 0,
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// bram interface (using clk)
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output [10:0] pixbuf_addr,
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input [ 8:0] pixbuf_data
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);
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parameter integer ROW_DEPTH = 128, BIT_DEPTH = 8;
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reg [31:0] counter = 0;
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reg [ 3:0] bcm_shift = 7; // which bit of the colors are we currently exposing.
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localparam integer StateInit = 0;
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localparam integer StateWriteRow = 1;
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localparam integer StateLatchout = 2;
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// the last data that we clock out for the row won't be exposed
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// in the next writerow state because we'll change addresses.
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localparam integer StateFinishExpose = 3;
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reg [7:0] state = StateInit; // our state
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// initial begin
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// state <= StateInit;
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// counter <= 0;
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// bcm_shift <= 7;
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// end
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// The FSM is a bit confusing since it's optimized for *speed*
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// We can basically display the previous line of data while we write the
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// next one. So instead of having WRITEROW -> LATCH -> EXPOSE
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// like most modules do, we can instead do (WRITEROW + EXPOSE_PREV) -> LATCH
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// There is an edge case for the first/last bits of the color depth.
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// When we start writing a line, we can't flash anything since there's no
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// previous. Likewise, when we end a line, we have to have an extra expose
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// period since there is no next writerow for this address. As a result,
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// we want to go MSB to LSB for our BCM so that the trailing expose time is
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// short!
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wire should_clock, should_expose;
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assign should_clock = (counter < ROW_DEPTH * 2 + 1); // the plus 1 is for the falling edge!
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assign should_expose = (counter < (16 << bcm_shift + 1)) && (bcm_shift != 7);
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reg [7:0] pixnum;
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assign pixbuf_addr = {bcm_shift, pixnum};
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always @(*) begin
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panel_rgb0 = pixbuf_data[2:0];
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panel_rgb1 = pixbuf_data[5:3];
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end
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always_ff @(posedge clk) begin
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counter <= counter + 1;
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case (state)
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StateInit: begin
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bcm_shift <= 7;
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counter <= 0;
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done <= 0;
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pixnum <= ROW_DEPTH - 1;
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// wait for the signal to write out our lines.
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if (write_trig) begin
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state <= StateWriteRow;
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end
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end
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StateWriteRow: begin
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if (should_clock) begin
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// we have data to clock
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display_clk <= counter[0];
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if (~counter[0]) begin
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// the data from the previous cycle is now ready.
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// panel_rgb0 <= pixbuf_data[2:0];
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// panel_rgb1 <= pixbuf_data[5:3];
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// write it out!
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end else begin
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// update the bram address so it's ready at the next clock cycle.
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pixnum <= pixnum - 1;
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end
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end
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if (should_expose) begin
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out_enable <= 0;
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end else begin
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out_enable <= 1;
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end
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// if we're done with our data clock out and also done with exposing
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// the previous line, go to the latchout stage.
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if (~should_clock && ~should_expose) begin
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counter <= 0;
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pixnum <= 0;
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state <= StateLatchout;
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display_clk <= 0;
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end
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end
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StateLatchout: begin
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// raise latch high; compute next bcm.
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latch <= 1;
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out_enable <= 1;
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pixnum <= ROW_DEPTH - 1;
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counter <= counter + 1;
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if (counter > 3) begin
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counter <= 0;
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if (bcm_shift == 0) begin
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// we've reached the lsb of this data, go to the next one!
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state <= StateFinishExpose;
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latch <= 0;
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end else begin
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bcm_shift <= bcm_shift - 1;
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state <= StateWriteRow;
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latch <= 0;
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end
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end
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end
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StateFinishExpose: begin
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assert (bcm_shift == 0);
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if (counter < (16 << bcm_shift)) begin
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out_enable <= 0;
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end else begin
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out_enable <= 1;
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state <= StateInit;
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done <= 1;
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// we are done!
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end
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end
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default: begin
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state <= StateInit;
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end
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endcase
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end
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endmodule
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