generated from saji/ecp5-template
67 lines
1.6 KiB
Systemverilog
67 lines
1.6 KiB
Systemverilog
module bitslicer (
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input clk,
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input [23:0] rgb0,
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input [23:0] rgb1,
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input [7:0] pixnum, // x-value of the pixels we are being fed.
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input start_write,
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output reg [5:0] bitplane_data,
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output [10:0] bitplane_addr,
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output reg bitplane_wren,
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output reg done
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);
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reg [2:0] bitplane_bit = 0;
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assign bitplane_addr = {bitplane_bit, pixnum};
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assign bitplane_data = {
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rgb1[bitplane_bit],
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rgb1[bitplane_bit+8],
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rgb1[bitplane_bit+16],
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rgb0[bitplane_bit],
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rgb0[bitplane_bit+8],
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rgb0[bitplane_bit+16]
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};
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reg [3:0] state = StateInit;
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localparam integer StateInit = 0;
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localparam integer StateWriteout = 1;
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localparam integer StateDone = 2;
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always @(posedge clk) begin
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case (state)
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StateInit: begin
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bitplane_bit <= 0;
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done <= 0;
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bitplane_wren <= 0;
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if (start_write) begin
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state <= StateWriteout;
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bitplane_wren <= 1;
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end
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end
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StateWriteout: begin
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// bitplane_data <= {
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// rgb[1][bitplane_bit],
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// rgb[1][bitplane_bit+8],
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// rgb[1][bitplane_bit+16],
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// rgb[0][bitplane_bit],
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// rgb[0][bitplane_bit+8],
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// rgb[0][bitplane_bit+16]
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// };
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bitplane_bit <= bitplane_bit + 1;
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if (bitplane_bit == 7) begin
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state <= StateDone;
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bitplane_wren <= 0;
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end
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end
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StateDone: begin
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done <= 1; // strobe
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state <= StateInit;
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end
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default: begin
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state <= StateInit;
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end
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endcase
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end
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endmodule
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