groovylight/verilog/tb/hub75e_tb.sv

`timescale 1ns / 100ps  // 1 ns time unit, 100 ps resolution
module hub75e_tb;

  reg clk;
  reg write_trig;

  wire [4:0] addr_out;
  wire [2:0] rgb0;
  wire [2:0] rgb1;
  wire display_clk;
  wire out_enable;
  wire latch;
  wire done;


  // block ram inputs
  reg [35:0] bram_data_in;
  reg [8:0] bram_addr_w;
  reg bram_write_en;


  wire [8:0] bram_addr_r;
  wire [35:0] bram_data_out;


  lineram bram (
    .din(bram_data_in),
    .addr_w(bram_addr_w),
    .dout(bram_data_out),
    .addr_r(bram_addr_r),
    .write_en(bram_write_en),
    .read_clk(clk),
    .write_clk(clk)
  );

  hub75e dut (
      .clk(clk),
      .write_trig(write_trig),
      .panel_rgb0(rgb0),
      .panel_rgb1(rgb1),
      .display_clk(display_clk),
      .out_enable(out_enable),
      .latch(latch),
      .done(done),

      .pixbuf_addr(bram_addr_r),
      .pixbuf_data(bram_data_out)
  );

  always #5 clk = !clk;
  initial begin
    $dumpfile("wave.vcd");
    $dumpvars(0, hub75e_tb);
    clk <= 0;
    bram_addr_w <= 0;
    bram_write_en <= 1;
    repeat (1) @(posedge clk);
    for (int i=0; i < 512; i=i+1) begin
      bram_data_in <= i + 5;
      bram_addr_w <= i;
      repeat (1) @(posedge clk);
    end
    bram_write_en <= 0;
    write_trig <= 1;
    repeat (2) @(posedge clk);
    write_trig <= 0;

    @(done);
    repeat (20) @(posedge clk);
    $finish();
  end
  initial begin
    repeat (500000) @(posedge clk);
    $finish();
  end
endmodule