generated from saji/ecp5-template
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No commits in common. "8e046b442aa5f91200420f32b828ee2198b4dd42" and "fe4a902bd87489f2e9e8bfc8a24fdf98f2a5b77c" have entirely different histories.
8e046b442a
...
fe4a902bd8
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@ -1,8 +1,9 @@
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from amaranth import Module, Cat, Mux, ShapeLike, Signal, Assert, unsigned
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from amaranth import Array, Module, Cat, Mux, ShapeLike, Signal, Assert, unsigned
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from amaranth.build import Platform
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from amaranth.lib import wiring, data
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from amaranth.lib.wiring import In, Out
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from amaranth.lib.memory import Memory, ReadPort, WritePort
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from amaranth.sim import Simulator
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from amaranth.utils import ceil_log2
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@ -17,7 +18,7 @@ class RGBLayout(data.StructLayout):
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)
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Rgb666Layout = RGBLayout(6, 6, 6)
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Rgb888Layout = RGBLayout(8, 8, 8)
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Rgb111Layout = RGBLayout(1, 1, 1)
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@ -112,31 +113,28 @@ class SwapBuffer(wiring.Component):
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shape=self.data_shape, depth=self.depth, init=[]
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)
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rd0 = self.bram0.read_port()
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wr0 = self.bram0.write_port()
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rd1 = self.bram1.read_port()
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wr1 = self.bram1.write_port()
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read0 = self.bram0.read_port()
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write0 = self.bram0.write_port()
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read1 = self.bram1.read_port()
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write1 = self.bram1.write_port()
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# for name, member in self.write_port.signature.members.items():
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# m.d.comb += self.write_port.members[name].eq(Mux(self.selector, write0[name], write1[name]))
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#
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m.d.comb += [
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# wr addres
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wr0.addr.eq(self.write_port.addr),
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wr1.addr.eq(self.write_port.addr),
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# write enables are based on selector
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wr0.en.eq(~self.selector),
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wr1.en.eq(self.selector),
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# connect write data. This is FINE because
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# there is one driver (the external writer)
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# and we en based on selector so the other one isn't active
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wr0.data.eq(self.write_port.data),
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wr1.data.eq(self.write_port.data),
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# connect rd address lines
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rd0.addr.eq(self.read_port.addr),
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rd1.addr.eq(self.read_port.addr),
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rd0.en.eq(~self.selector),
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rd1.en.eq(self.selector),
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# we do this because the read_data lines are driven, this prevents
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# double-driver situations even though we en using selector above
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self.read_port.data.eq(Mux(self.selector, rd1.data, rd0.data)),
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write0.addr.eq(self.write_port.addr),
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write1.addr.eq(self.write_port.addr),
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write0.en.eq(~self.selector),
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write1.en.eq(self.selector),
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# self.write_port.data.eq(Mux(self.selector, write0.data, write1.data)),
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write0.data.eq(self.write_port.data),
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write1.data.eq(self.write_port.data),
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read0.addr.eq(self.read_port.addr),
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read1.addr.eq(self.read_port.addr),
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read0.en.eq(~self.selector),
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read1.en.eq(self.selector),
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self.read_port.data.eq(Mux(self.selector, read1.data, read0.data)),
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]
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return m
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@ -148,48 +146,33 @@ class Hub75StringDriver(wiring.Component):
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it should send.
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"""
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bcm_select: In(3)
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done: Out(1)
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start: In(1)
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bram_port: In(ReadPort.Signature(addr_width=9, shape=Rgb888Layout))
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display_out: Out(Hub75Data()) # data signal output.
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def __init__(self, panel_length: int = 128, *, src_loc_at=0):
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self.panel_length = panel_length
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super().__init__(
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{
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"bcm_select": In(3),
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"done": Out(1),
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"start": In(1),
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"bram_port": In(
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ReadPort.Signature(
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addr_width=ceil_log2(panel_length),
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shape=data.ArrayLayout(Rgb666Layout, 2),
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)
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),
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"display_out": Out(Hub75Data()),
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},
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src_loc_at=src_loc_at,
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)
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super().__init__(None, src_loc_at=src_loc_at)
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def elaborate(self, platform: Platform) -> Module:
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m = Module()
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self._counter = counter = Signal(32) # unused count is optimized out
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# add two memories
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self._counter = counter = Signal(32)
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m.d.sync += counter.eq(counter + 1)
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ram_rgb0_slice = Cat(
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self.bram_port.data[0]["red"].bit_select(self.bcm_select, 1),
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self.bram_port.data[0]["blue"].bit_select(self.bcm_select, 1),
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self.bram_port.data[0]["green"].bit_select(self.bcm_select, 1),
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ram_rgb_slice = Cat(
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self.bram_port.data["red"].bit_select(self.bcm_select, 1),
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self.bram_port.data["blue"].bit_select(self.bcm_select, 1),
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self.bram_port.data["green"].bit_select(self.bcm_select, 1),
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)
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ram_rgb1_slice = Cat(
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self.bram_port.data[1]["red"].bit_select(self.bcm_select, 1),
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self.bram_port.data[1]["blue"].bit_select(self.bcm_select, 1),
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self.bram_port.data[1]["green"].bit_select(self.bcm_select, 1),
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)
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m.d.comb += [
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self.display_out.rgb0.eq(ram_rgb0_slice),
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self.display_out.rgb1.eq(ram_rgb1_slice),
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]
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m.d.sync += Assert(self.bcm_select < 6)
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pixnum = Signal(ceil_log2(self.panel_length), init=self.panel_length - 1)
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m.d.comb += self.bram_port.addr.eq(pixnum)
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pixnum = Signal(range(self.panel_length), init=self.panel_length - 1)
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pixrow = Signal(1, init=0)
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m.d.comb += self.bram_port.addr.eq(Cat(pixrow, pixnum))
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with m.FSM():
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with m.State("init"):
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@ -197,22 +180,42 @@ class Hub75StringDriver(wiring.Component):
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self.done.eq(0),
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counter.eq(0),
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pixnum.eq(self.panel_length - 1),
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pixrow.eq(0),
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]
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with m.If(self.start == 1):
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m.d.sync += self.bram_port.en.eq(1)
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m.next = "writerow"
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with m.State("prefetch"):
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with m.If(counter == 0):
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m.d.sync += pixrow.eq(0)
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with m.Elif(counter == 1):
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m.d.sync += pixrow.eq(1)
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with m.Elif(counter == 2):
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m.d.sync += self.display_out.rgb0.eq(ram_rgb_slice)
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with m.Elif(counter == 3):
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m.d.sync += [self.display_out.rgb1.eq(ram_rgb_slice), counter.eq(0)]
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m.next = "writerow"
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with m.State("writerow"):
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with m.If(counter[0] == 0):
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# do nothing
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pass
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with m.If(counter[0:1] == 0):
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# rising edge of the clock
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m.d.sync += pixrow.eq(0)
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with m.If((counter[0] == 1) & (pixnum != 0)):
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m.d.sync += pixnum.eq(pixnum - 1)
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with m.If(counter[0:1] == 1):
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m.d.sync += [
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pixrow.eq(1),
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self.display_out.rgb0.eq(ram_rgb_slice),
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]
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with m.If(counter[0:1] == 2):
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m.d.sync += [
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pixnum.eq(pixnum - 1),
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pixrow.eq(0),
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self.display_out.rgb1.eq(ram_rgb_slice),
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]
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with m.If(counter == 128 * 2 + 1):
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with m.Else():
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m.next = "done"
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with m.State("done"):
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m.d.sync += [self.done.eq(1), self.bram_port.en.eq(0)]
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m.d.sync += self.done.eq(1)
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m.next = "init"
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return m
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@ -223,40 +226,10 @@ class Hub75Coordinator(wiring.Component):
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def __init__(self, n_strings=1):
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self.n_strings = n_strings
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super().__init__(
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{
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"ctrl": Out(Hub75Ctrl),
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"data": data.ArrayLayout(Hub75Data, n_strings),
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# TODO: fetching routine? maybe it's passed through.
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}
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)
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super().__init__()
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def elaborate(self, platform: Platform) -> Module:
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m = Module()
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# swapline is which buffer we are using vs sending out.
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swapline = Signal(1)
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# for each string, spawn a swapbuffer + stringdriver and connect.
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# don't worry about fetching for now.
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self.strings = strings = []
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self.buffers = bufs = []
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donearr = []
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startStrings = Signal(1)
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stringsDone = Signal(1)
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for i in range(self.n_strings):
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sb = SwapBuffer(depth=128, shape=data.ArrayLayout(Rgb666Layout, 2))
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bufs += sb
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stringdriver = Hub75StringDriver(128)
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strings += stringdriver
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wiring.connect(m, sb.read_port, stringdriver.bram_port)
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m.d.comb += [
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self.data[i].eq(stringdriver.display_out),
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stringdriver.start.eq(startStrings),
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sb.selector.eq(swapline),
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]
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m.submodules += [sb, stringdriver]
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donearr += stringdriver.done
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m.d.comb += stringsDone.eq(Cat(*donearr).all())
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return m
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@ -266,10 +239,6 @@ class Hub75EDriver(wiring.Component):
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This version is faster than most implementations by merging the exposure
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period and the data-write period to happen simultaneously. As a result,
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the display can be brighter due to higher duty cycle.
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NOTICE: this is a direct port of the old verilog code. It isn't up to date with the
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modified structure. Notably, it uses RGB888 with double-fetch (4xclocking)
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"""
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start: In(1)
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@ -1,124 +0,0 @@
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# Geometry-related classes and functions. Manipulations and
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# generation of panel-layout metadata for use in the HDL.
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from enum import Enum
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from dataclasses import dataclass
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@dataclass(frozen=True, order=True)
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class Coord:
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"""Coordinate class. Uses computer-graphics standard coordinate system,
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where X=0, Y=0 is top left. +X goes right. +Y goes down.
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"""
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x: int
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y: int
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def __post_init__(self):
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if self.x < 0 or self.y < 0:
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raise RuntimeError("x and y must both be >= 0")
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@dataclass(frozen=True)
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class BBox:
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"""Bounding box class. Captures the top left coordinate and bottom right coordinate
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of an object"""
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topleft: Coord
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bottomright: Coord
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def __post_init__(self):
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if not self.topleft < self.bottomright:
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raise RuntimeError("topleft must be strictly less than bottomright")
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def contains(self, c: Coord) -> bool:
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return c > self.topleft and c < self.bottomright
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@dataclass(frozen=True)
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class DisplayDimensions:
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"""Represents the dimensions of a display string, in length x height. Notably
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this is in local coordinates to the display. The display top left is 0,0.
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Uses length/height notation to separate it from coord
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"""
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length: int
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height: int
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class DisplayRotation(Enum):
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"""Display rotation enums. The names indicate the general direction
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of data flow. most normal displays (LCDs, CRTs) are LEFTRIGHT,
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since they scan left-to-right, top to bottom.
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Note that the direction of subsequent lines is not always clear.
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They are enumerated below:
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LEFTRIGHT -> next line is below it (-Y)
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UPDOWN -> next line is to the LEFT (-X)
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DOWNUP -> next line is to the RIGHT (+X)
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RIGHTLEFT -> next line is above it (+Y)
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Generally, prefer LEFTRIGHT/UPDOWN over other rotations.
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"""
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LEFTRIGHT = 0
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UPDOWN = 1
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DOWNUP = 2
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RIGHTLEFT = 3 # why are you like this.
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@dataclass(frozen=True)
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class _DisplayString:
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"""Internal class to represent a string of HUB75 displays.
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position: (X,Y) coordinates of the local top-left of the display
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dimensions: (length, height) local-coordinate dimensions of the display.
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rotation: DisplayRotation: the orientation of the display.
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"""
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position: Coord
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dimensions: DisplayDimensions
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rotation: DisplayRotation
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@property
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def bbox(self) -> BBox:
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"""Returns the bounding box of the display based on the dimensions, position, and rotation."""
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x = self.position.x
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y = self.position.y
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l = self.dimensions.length
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h = self.dimensions.height
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match self.rotation:
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case DisplayRotation.LEFTRIGHT:
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return BBox(Coord(x, y), Coord(x + l, y + h))
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case DisplayRotation.UPDOWN:
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return BBox(Coord(x - h, y), Coord(x, y + l))
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case DisplayRotation.DOWNUP:
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return BBox(Coord(x, y + l), Coord(x + h, y))
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case DisplayRotation.RIGHTLEFT:
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return BBox(Coord(x - l, y - h), Coord(x, y))
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def contains_pix(self, coord: Coord) -> bool:
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"""Checks if the given coordinate is inside this display."""
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return self.bbox.contains(coord)
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class DisplayGeometry:
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"""Represents a display based on several strings in different positions.
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"""
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def __init__(self, *, strict: bool = False):
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self.strict = strict
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pass
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def add_string(self, position: (int, int), rot: int, dimensions: (int, int)):
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"""Add a new string to the display. This new string is located at
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a specific point, and has a direction, along with dimension that reveal
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the number of address lines (typically 64, with 1:32 selection so 5 address
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bits) and the total length of the string which is used to size the line
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buffers.
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When in strict mode, this method may throw an exception if this new string
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will overlap with an existing string.
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"""
|
12
src/groovylight/lineram.py
Normal file
12
src/groovylight/lineram.py
Normal file
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@ -0,0 +1,12 @@
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from amaranth import Module, Cat, Signal, Assert, unsigned
|
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from amaranth.build import Platform
|
||||
|
||||
from amaranth.lib import wiring, data
|
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from amaranth.lib.wiring import In, Out
|
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from amaranth.lib.memory import Memory
|
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# file to wrap line ram using PDPw16KD
|
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# this is tricky.
|
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|
||||
|
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def lineram():
|
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return Memory(shape=unsigned(24), depth=512)
|
|
@ -5,7 +5,7 @@ from amaranth.lib.wiring import In, Out
|
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from amaranth.lib.memory import Memory, WritePort
|
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from amaranth.sim import Simulator
|
||||
|
||||
from .bitslicer import Hub75StringDriver, Rgb666Layout
|
||||
from .bitslicer import Hub75StringDriver, Rgb888Layout
|
||||
|
||||
|
||||
def test_stringdriver():
|
||||
|
@ -15,9 +15,7 @@ def test_stringdriver():
|
|||
# 3. slice the correct bit from the data.
|
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m = Module()
|
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m.submodules.dut = dut = Hub75StringDriver()
|
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m.submodules.mem = mem = Memory(
|
||||
shape=data.ArrayLayout(Rgb666Layout, 2), depth=128, init=[]
|
||||
)
|
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m.submodules.mem = mem = Memory(shape=Rgb888Layout, depth=512, init=[])
|
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port = mem.read_port()
|
||||
|
||||
wiring.connect(m, port, dut.bram_port)
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|
@ -28,11 +26,12 @@ def test_stringdriver():
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ctx.set(dut.start, 1)
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await ctx.tick()
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ctx.set(dut.start, 0)
|
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assert ctx.get(dut.bram_port.en) == 1
|
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assert(ctx.get(dut.bram_port.en) == 1)
|
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pass
|
||||
|
||||
sim = Simulator(m)
|
||||
sim.add_clock(1e-6)
|
||||
|
||||
with sim.write_vcd("output.vcd"):
|
||||
|
||||
sim.run_until(1e-6 * 1000)
|
||||
|
|
|
@ -5,11 +5,11 @@ from amaranth.lib.wiring import In, Out
|
|||
from amaranth.lib.memory import Memory, WritePort
|
||||
from amaranth.sim import Simulator
|
||||
|
||||
from .bitslicer import Hub75StringDriver, Rgb666Layout, SwapBuffer
|
||||
from .bitslicer import Hub75StringDriver, Rgb888Layout, SwapBuffer
|
||||
|
||||
|
||||
def test_swapbuffer():
|
||||
dut = SwapBuffer(Rgb666Layout, 512)
|
||||
dut = SwapBuffer(Rgb888Layout, 512)
|
||||
sim = Simulator(dut)
|
||||
sim.add_clock(1e-6)
|
||||
|
||||
|
|
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Reference in a new issue