generated from saji/ecp5-template
Compare commits
4 commits
5f54b8acd8
...
09485a9753
Author | SHA1 | Date | |
---|---|---|---|
saji | 09485a9753 | ||
saji | 300e8192fe | ||
saji | dd334e8bad | ||
saji | ae1ad4633c |
|
@ -31,22 +31,22 @@ ip = "dhcp" # Can also be e.g. "192.168.0.123"
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strict = true # allows some wacky configurations, like panels that overlap.
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[[display.strings]]
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position = { x = 64, y = 0 }
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position = { x = 0, y = 0 }
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dimensions = { length = 256, height = 64 }
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rotation = "UPDOWN"
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rotation = "R90"
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[[display.strings]]
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position = { x = 65, y = 0 }
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dimensions = { length = 256, height = 64 }
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rotation = "LEFTRIGHT"
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rotation = "R0"
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[[display.strings]]
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position = { x = 65, y = 65 }
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dimensions = { length = 256, height = 64 }
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rotation = "LEFTRIGHT"
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rotation = "R0"
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[[display.strings]]
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position = { x = 65, y = 130 }
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dimensions = { length = 256, height = 64 }
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rotation = "LEFTRIGHT"
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rotation = "R0"
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[[display.strings]]
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position = { x = 65, y = 195 }
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dimensions = { length = 256, height = 64 }
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rotation = "LEFTRIGHT"
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rotation = "R0"
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14
pdm.lock
14
pdm.lock
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@ -5,7 +5,7 @@
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groups = ["default", "dev"]
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strategy = ["inherit_metadata"]
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lock_version = "4.5.0"
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content_hash = "sha256:fbfe1db54d73aa2641413610d5e62d87b02de247293e2af3cd53ee0c283318db"
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content_hash = "sha256:70036fd7ee1fe6910ed441a5419d9194d1abc592cbf2f39deb1d7a8e77501d03"
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[[metadata.targets]]
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requires_python = "==3.12.*"
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@ -39,6 +39,18 @@ dependencies = [
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"amaranth<0.7,>=0.4",
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]
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[[package]]
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name = "amaranth-soc"
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version = "0.1a1.dev24"
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requires_python = "~=3.9"
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git = "https://github.com/amaranth-lang/amaranth-soc.git"
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revision = "5c43cf58f15d9cd9c69ff83c97997708d386b2dc"
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summary = "System on Chip toolkit for Amaranth HDL"
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groups = ["default"]
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dependencies = [
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"amaranth<0.6,>=0.5",
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]
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[[package]]
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name = "basedpyright"
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version = "1.18.0"
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@ -8,6 +8,7 @@ authors = [
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dependencies = [
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"amaranth>=0.5.1",
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"amaranth-boards @ git+https://github.com/amaranth-lang/amaranth-boards.git",
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"amaranth-soc @ git+https://github.com/amaranth-lang/amaranth-soc.git",
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]
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requires-python = "==3.12.*"
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readme = "README.md"
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@ -2,13 +2,13 @@
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# to know its location.
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# during operation, it is given a row index, and responds with the data.
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from amaranth import Module, Signal, unsigned, Cat
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from amaranth import Module, Signal, unsigned
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from amaranth.build import Platform
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from amaranth.lib import wiring, data
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from amaranth.lib.wiring import In, Out
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from amaranth.lib import stream
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import logging
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from itertools import pairwise
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from .common import Rgb888Layout
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from .geom import DisplayString
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@ -16,7 +16,6 @@ from .geom import DisplayString
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logger = logging.getLogger(__name__)
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# FIXME: sizing should be based off of screen size.
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CoordLayout = data.StructLayout({"x": unsigned(10), "y": unsigned(10)})
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@ -53,7 +52,7 @@ class AddressGenerator(wiring.Component):
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self.geom = geom
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super().__init__(
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{
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"coordstream": Out(
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"output": Out(
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stream.Signature(data.ArrayLayout(CoordLayout, geom.dimensions.mux))
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),
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"start": In(1),
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@ -75,41 +74,60 @@ class AddressGenerator(wiring.Component):
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m.d.comb += translate.input_x.eq(counter)
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m.d.comb += translate.addr.eq(addr)
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m.d.comb += self.coordstream.payload.eq(translate.output)
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m.d.comb += self.output.payload.eq(translate.output)
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with m.FSM():
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with m.State("init"):
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m.d.comb += [self.done.eq(0), self.coordstream.valid.eq(0)]
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m.d.comb += [self.done.eq(0), self.output.valid.eq(0)]
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m.d.sync += [counter.eq(0), addr.eq(self.addr)]
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with m.If(self.start):
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m.next = "run"
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with m.State("run"):
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m.d.comb += self.coordstream.valid.eq(1)
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m.d.comb += self.output.valid.eq(1)
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# stream data out as long as it's valid.
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with m.If(
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self.coordstream.ready
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& (counter == self.geom.dimensions.length - 1)
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self.output.ready & (counter == self.geom.dimensions.length - 1)
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):
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m.next = "done"
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with m.Elif(self.coordstream.ready):
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with m.Elif(self.output.ready):
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m.d.sync += counter.eq(counter + 1)
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pass
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with m.State("done"):
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m.d.comb += self.coordstream.valid.eq(0)
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m.d.comb += self.output.valid.eq(0)
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m.d.comb += self.done.eq(1)
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m.next = "init"
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return m
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def example_rgb_transform(x, y):
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"""A simple coordinate-RGB transformation that computes RGB values directly from the x-y position
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of the pixel. This is used in the simple case and as a test for the rest of the system."""
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return {
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"red": x + y,
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"green": x - y,
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"blue": x ^ y,
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}
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class BasicFetcher(wiring.Component):
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"""A generic function-based fetcher. Takes a function of the form f(x,y: int) -> RGB."""
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"""A generic function-based fetcher. Takes a function of the form f(x,y: int) -> dict rgb values.
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If no function is provided it uses a basic coordinate-driven rgb transform where red = x+y,
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green = x - y, and blue = x ^ y.
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When providing a function, it must return a dictionary with the keys "red", "green", "blue"."""
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def __init__(
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self, geom: DisplayString, dfunc, data_shape=Rgb888Layout, *, src_loc_at=0
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self,
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geom: DisplayString,
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dfunc=example_rgb_transform,
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data_shape=Rgb888Layout,
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*,
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src_loc_at=0,
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):
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self.geom = geom
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self.dfunc = dfunc
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@ -118,7 +136,7 @@ class BasicFetcher(wiring.Component):
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"input": In(
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stream.Signature(data.ArrayLayout(CoordLayout, geom.dimensions.mux))
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),
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"pixstream": Out(
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"output": Out(
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stream.Signature(data.ArrayLayout(data_shape, geom.dimensions.mux))
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),
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},
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@ -128,20 +146,25 @@ class BasicFetcher(wiring.Component):
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def elaborate(self, platform: Platform) -> Module:
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m = Module()
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# test mode - pass through, r = x + y, g = x - y, b = {y,x}
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colors = self.pixstream.payload
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colors = self.output.payload
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m.d.comb += [
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self.input.valid.eq(self.pixstream.valid),
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self.input.ready.eq(self.pixstream.ready),
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self.output.valid.eq(self.input.valid),
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self.input.ready.eq(self.output.ready),
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]
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for i in range(self.geom.dimensions.mux):
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inp = self.input.payload[i]
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output = self.dfunc(inp.x, inp.y)
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m.d.comb += [
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colors[i].red.eq(inp.x + inp.y),
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colors[i].green.eq(inp.x - inp.y),
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colors[i].blue.eq(inp.x ^ inp.y),
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colors[i].red.eq(output["red"]),
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colors[i].green.eq(output["green"]),
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colors[i].blue.eq(output["blue"]),
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]
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return m
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def chain_streams(m, streams):
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"""For "stream combinators", this allows you to easily chain outputs to inputs."""
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for pair in pairwise(streams):
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wiring.connect(m, pair[0].output, pair[1].input)
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@ -210,6 +210,9 @@ class DisplayGeometry:
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sum += s.dimensions.size
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return sum
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@property
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def strings(self) -> [DisplayString]:
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return self._strings
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def add_string(self, s: DisplayString):
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"""Add a new string to the display.
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|
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@ -3,9 +3,12 @@ from amaranth.build import Platform
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from amaranth.lib import wiring, data
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from amaranth.lib.wiring import In, Out
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from amaranth.lib.memory import Memory, ReadPort, WritePort
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from amaranth_soc import wishbone
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from amaranth.utils import ceil_log2
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import logging
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from groovylight.geom import DisplayGeometry
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from .common import Rgb666Layout, Hub75Stream, Hub75Ctrl, Hub75Data, Rgb888Layout
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@ -34,10 +37,10 @@ class SwapBuffer(wiring.Component):
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super().__init__(
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{
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"selector": In(1),
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"read_port": In(
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"read_port": Out(
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ReadPort.Signature(addr_width=ceil_log2(depth), shape=shape)
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),
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"write_port": In(
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"write_port": Out(
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WritePort.Signature(addr_width=ceil_log2(depth), shape=shape)
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),
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}
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@ -313,14 +316,16 @@ class Hub75DataDriver(wiring.Component):
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return m
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class Hub75Coordinator(wiring.Component):
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"""A shared-control hub75 driver"""
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def __init__(self, n_strings=1):
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self.n_strings = n_strings
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def __init__(self, geom: DisplayGeometry, *, double_fetch=True):
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self.geom = geom
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self.double_fetch = double_fetch
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super().__init__(
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{
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"hub75": Out(Hub75Ctrl(n_strings)),
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"hub75": Out(Hub75Ctrl(self.geom.n_strings)),
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# TODO: fetching routine? maybe it's passed through.
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}
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)
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@ -337,34 +342,38 @@ class Hub75Coordinator(wiring.Component):
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donearr = []
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startStrings = Signal(1)
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stringsDone = Signal(1)
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bram_shape = Rgb888Layout if self.double_fetch else data.ArrayLayout(Rgb888Layout, 2)
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for i in range(self.n_strings):
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sb = SwapBuffer(depth=128, shape=data.ArrayLayout(Rgb666Layout, 2))
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for idx, string in enumerate(self.geom.strings):
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mdepth = string.dimensions.length
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if self.double_fetch:
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mdepth = mdepth * 2
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sb = SwapBuffer(depth=mdepth, shape=bram_shape)
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bufs.append(sb)
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stringdriver = Hub75DataDriver(
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128, data_shape=Rgb666Layout, double_fetch=False
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string.dimensions.length,
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data_shape=Rgb888Layout,
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double_fetch=self.double_fetch,
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)
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strings.append(stringdriver)
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wiring.connect(m, sb.read_port, stringdriver.bram_port)
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wiring.connect(m, sb.read_port, stringdriver.bram)
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# wiring.connect(m, self.hub75.data[idx], stringdriver.data.flip())
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m.d.comb += [
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self.data[i].eq(stringdriver.display_out),
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self.hub75.data[idx].rgb0.eq(stringdriver.data.rgb0),
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self.hub75.data[idx].rgb1.eq(stringdriver.data.rgb1),
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stringdriver.start.eq(startStrings),
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sb.selector.eq(swapline),
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]
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m.submodules += [sb, stringdriver]
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donearr.append(stringdriver.done)
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# combine the done signals into one signal with AND-reduction
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m.d.comb += stringsDone.eq(Cat(*donearr).all())
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self.addr = Signal(5)
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# handle the fetch side.
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# WIP: pass in fetcher/pixgen/geometry.
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# right now we assume that it's just one panel,
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# address is (string_number, hi/lo, addr)
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for i in range(self.n_strings):
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lookup_addr = Cat(i, self.addr, 0)
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# generate a sequence of transfers.
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# right now we're just going to use a basicFetcher
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# TODO: support SDRAM framebuffer
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with m.FSM():
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with m.State("init"):
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|
@ -384,131 +393,3 @@ class Hub75Coordinator(wiring.Component):
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# fetch line
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#
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class Hub75EDriver(wiring.Component):
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"""An optimized driver for hub75 strings.
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This version is faster than most implementations by merging the exposure
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period and the data-write period to happen simultaneously. As a result,
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the display can be brighter due to higher duty cycle.
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NOTICE: this is a direct port of the old verilog code. It isn't up to date with the
|
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modified structure. Notably, it uses RGB888 with double-fetch (4xclocking)
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"""
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start: In(1)
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done: Out(1)
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out: Out(Hub75Stream())
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buf_addr: Out(9)
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buf_data: In(36)
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row_depth = 128
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bit_depth = 8
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bcm_len = 32
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def elaborate(self, platform: Platform) -> Module:
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m = Module()
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counter = Signal(32)
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bcm_shift: Signal = Signal(4, init=7)
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m.d.sync += counter.eq(counter + 1)
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# construct helper signals.
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ram_r = self.buf_data[16:23]
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ram_b = self.buf_data[8:15]
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ram_g = self.buf_data[0:7]
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ram_rgb_slice = Cat(
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ram_r.bit_select(bcm_shift, 1),
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ram_g.bit_select(bcm_shift, 1),
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ram_b.bit_select(bcm_shift, 1),
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)
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pixnum = Signal(8, reset=127)
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pixrow = Signal(1, reset=0)
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m.d.comb += self.buf_addr.eq(Cat(pixrow, pixnum))
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should_clock = counter < (128 * 2 + 1)
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should_expose = (counter < (32 << (bcm_shift + 1) + 1)).bool() & (
|
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bcm_shift != 7
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).bool()
|
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|
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with m.FSM():
|
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with m.State("init"):
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m.d.sync += [
|
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bcm_shift.eq(7),
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counter.eq(0),
|
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self.done.eq(0),
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pixnum.eq(127),
|
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pixrow.eq(0),
|
||||
]
|
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with m.If(self.start == 1):
|
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m.next = "prefetch"
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with m.State("prefetch"):
|
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with m.If(counter == 0):
|
||||
m.d.sync += pixrow.eq(0)
|
||||
with m.Elif(counter == 1):
|
||||
m.d.sync += pixrow.eq(1)
|
||||
with m.Elif(counter == 2):
|
||||
m.d.sync += self.out.rgb0.eq(ram_rgb_slice)
|
||||
with m.Elif(counter == 3):
|
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m.d.sync += [self.out.rgb1.eq(ram_rgb_slice), counter.eq(0)]
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m.next = "writerow"
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with m.State("writerow"):
|
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# expose if we haven't done it for long enough yet.
|
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m.d.sync += self.out.oe.eq(~(should_expose))
|
||||
with m.If(should_clock):
|
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# clock is high on entry
|
||||
m.d.sync += self.out.display_clk.eq(counter[1] == 0)
|
||||
|
||||
with m.If(counter[0:1] == 0):
|
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# rising edge of the clock
|
||||
m.d.sync += pixrow.eq(0)
|
||||
|
||||
with m.If(counter[0:1] == 1):
|
||||
m.d.sync += [
|
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pixrow.eq(1),
|
||||
self.out.rgb0.eq(ram_rgb_slice),
|
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]
|
||||
with m.If(counter[0:1] == 2):
|
||||
m.d.sync += [
|
||||
pixnum.eq(pixnum - 1),
|
||||
pixrow.eq(0),
|
||||
self.out.rgb1.eq(ram_rgb_slice),
|
||||
]
|
||||
|
||||
with m.Elif(~(should_expose)):
|
||||
# we are done both feeding in the new data and exposing the previous.
|
||||
m.d.sync += [counter.eq(0), self.out.display_clk.eq(0)]
|
||||
m.next = "latchout"
|
||||
with m.State("latchout"):
|
||||
m.d.sync += [
|
||||
pixnum.eq(127),
|
||||
self.out.latch.eq(1),
|
||||
]
|
||||
with m.If(counter > 3):
|
||||
m.d.sync += self.out.latch.eq(0)
|
||||
m.d.sync += counter.eq(0)
|
||||
with m.If(bcm_shift == 0):
|
||||
m.next = "finish"
|
||||
with m.Else():
|
||||
m.d.sync += bcm_shift.eq(bcm_shift - 1)
|
||||
m.next = "prefetch"
|
||||
|
||||
with m.State("finish"):
|
||||
m.d.sync += Assert(bcm_shift == 0, "finish without bcm shift 0")
|
||||
|
||||
with m.If(counter < (32)):
|
||||
m.d.sync += self.out.oe.eq(0)
|
||||
with m.Else():
|
||||
m.d.sync += [self.out.oe.eq(1), self.done.eq(1)]
|
||||
m.next = "init"
|
||||
|
||||
return m
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
m = Hub75EDriver()
|
||||
from amaranth.cli import main
|
||||
|
||||
main(m)
|
||||
|
|
|
@ -1,8 +1,10 @@
|
|||
# main entry point for CLI applications.
|
||||
|
||||
import logging
|
||||
import os
|
||||
import argparse
|
||||
from groovylight.config import Config
|
||||
from groovylight.platforms.cxxrtl_sim import emit_cxxrtl
|
||||
|
||||
logger = logging.getLogger(__loader__.name)
|
||||
|
||||
|
@ -18,9 +20,21 @@ def setup_logger(args):
|
|||
handler.setFormatter(formatter)
|
||||
|
||||
root_logger.addHandler(handler)
|
||||
if args.log_file is not None:
|
||||
hdlr = logging.FileHandler(args.log_file)
|
||||
hdlr.setFormatter(formatter)
|
||||
root_logger.addHandler(formatter)
|
||||
|
||||
root_logger.setLevel(args.loglevel)
|
||||
|
||||
|
||||
def dir_path(string):
|
||||
if os.path.isdir(string):
|
||||
return string
|
||||
else:
|
||||
raise NotADirectoryError(string)
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser()
|
||||
|
||||
|
@ -41,6 +55,9 @@ def main():
|
|||
type=argparse.FileType("w"),
|
||||
metavar="FILE",
|
||||
)
|
||||
parser.add_argument(
|
||||
"-D", "--dump", help="Dump verilog to folder", type=dir_path, metavar="FOLDER"
|
||||
)
|
||||
|
||||
parser.add_argument(
|
||||
"config",
|
||||
|
@ -54,8 +71,17 @@ def main():
|
|||
setup_logger(args)
|
||||
|
||||
conf = Config(args.config)
|
||||
print(conf)
|
||||
|
||||
# use the config to create the module.
|
||||
|
||||
if conf.conf["hardware"]["type"] == "cxxrtl":
|
||||
logger.info("Generating CXXRTL based graphical simulator.")
|
||||
emit_cxxrtl(conf)
|
||||
|
||||
elif conf.conf["hardware"]["type"] == "colorlight":
|
||||
logger.debug("Generating colorlight code")
|
||||
if args.dump:
|
||||
logger.info(f"Dumping verilog to {args.dump}")
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
|
|
|
@ -7,3 +7,16 @@
|
|||
# black box the UDP streaming.
|
||||
# provide code for display outputs to render onto SDL2 canvas.
|
||||
# compile code (optionally)
|
||||
from amaranth.back import cxxrtl
|
||||
from amaranth import Module
|
||||
|
||||
from groovylight import hub75
|
||||
|
||||
|
||||
|
||||
def emit_cxxrtl(config):
|
||||
m = Module()
|
||||
m.submodules.coordinator = crd = hub75.Hub75Coordinator(config.geom)
|
||||
cxxrtl.convert(m, ports=[])
|
||||
|
||||
|
||||
|
|
|
@ -1,10 +1,9 @@
|
|||
from amaranth.lib import wiring, data
|
||||
from amaranth import Module
|
||||
from amaranth.lib import wiring
|
||||
from amaranth.sim import Simulator
|
||||
import random
|
||||
from random import randrange
|
||||
import pytest
|
||||
|
||||
from groovylight.fetcher import AddressConverter, AddressGenerator, BasicFetcher
|
||||
from groovylight.fetcher import AddressConverter, AddressGenerator, BasicFetcher, chain_streams
|
||||
from groovylight.geom import DisplayString, Coord, DisplayDimensions, DisplayRotation
|
||||
|
||||
ds_testdata = [
|
||||
|
@ -82,7 +81,7 @@ def test_generator(addr, rot):
|
|||
|
||||
async def stream_checker(ctx):
|
||||
while ctx.get(dut.done) == 0:
|
||||
payload = await stream_get(ctx, dut.coordstream)
|
||||
payload = await stream_get(ctx, dut.output)
|
||||
assert expected.pop() == payload
|
||||
|
||||
sim.add_testbench(runner)
|
||||
|
@ -103,12 +102,12 @@ def test_basic_fetcher(inp, expected):
|
|||
ds = DisplayString(
|
||||
Coord(3, 0), DisplayDimensions(128, 64, mux=1), DisplayRotation.R0
|
||||
)
|
||||
dut = BasicFetcher(ds, None)
|
||||
dut = BasicFetcher(ds)
|
||||
sim = Simulator(dut)
|
||||
|
||||
async def test(ctx):
|
||||
ctx.set(dut.input.payload[0], inp)
|
||||
res = ctx.get(dut.pixstream.payload)[0]
|
||||
res = ctx.get(dut.output.payload)[0]
|
||||
assert res["red"] == expected["red"]
|
||||
assert res["green"] == expected["green"]
|
||||
assert res["blue"] == expected["blue"]
|
||||
|
@ -117,3 +116,34 @@ def test_basic_fetcher(inp, expected):
|
|||
|
||||
with sim.write_vcd("fetcher.vcd"):
|
||||
sim.run()
|
||||
|
||||
|
||||
|
||||
def test_stream_e2e():
|
||||
ds = DisplayString(
|
||||
Coord(3, 0), DisplayDimensions(128, 64, mux=1), DisplayRotation.R0
|
||||
)
|
||||
m = Module()
|
||||
m.submodules.gen = addrgen = AddressGenerator(ds)
|
||||
m.submodules.fetch = fetch = BasicFetcher(ds)
|
||||
|
||||
chain_streams(m, [addrgen, fetch])
|
||||
|
||||
sim = Simulator(m)
|
||||
sim.add_clock(1e-6)
|
||||
|
||||
async def stim(ctx):
|
||||
await ctx.tick()
|
||||
ctx.set(addrgen.start, 1)
|
||||
await ctx.tick()
|
||||
ctx.set(addrgen.start, 0)
|
||||
payload = await stream_get(ctx, fetch.output)
|
||||
assert payload[0] == {"red": 3, "green": 3, "blue": 3}
|
||||
|
||||
|
||||
sim.add_testbench(stim)
|
||||
|
||||
with sim.write_vcd("stream_e2e.vcd"):
|
||||
sim.run()
|
||||
|
||||
|
||||
|
|
|
@ -7,6 +7,7 @@ from random import randrange
|
|||
import pytest
|
||||
|
||||
from groovylight.common import Rgb888Layout, Rgb666Layout
|
||||
from groovylight.geom import DisplayGeometry, DisplayString, DisplayRotation, DisplayDimensions, Coord
|
||||
|
||||
from groovylight.hub75 import (
|
||||
DisplayClock,
|
||||
|
@ -146,10 +147,13 @@ def test_datadriver_single(bcm):
|
|||
with sim.write_vcd("output.vcd"):
|
||||
sim.run()
|
||||
|
||||
@pytest.mark.skip()
|
||||
|
||||
def test_hub75_coordinator():
|
||||
m = Module()
|
||||
m.submodules.dut = dut = Hub75Coordinator(1)
|
||||
geom = DisplayGeometry()
|
||||
geom.add_string(DisplayString(Coord(0,0), DisplayDimensions(128,64), DisplayRotation.R0))
|
||||
geom.add_string(DisplayString(Coord(65,0), DisplayDimensions(128,64), DisplayRotation.R0))
|
||||
m.submodules.dut = dut = Hub75Coordinator(geom)
|
||||
|
||||
sim = Simulator(m)
|
||||
sim.add_clock(1e-6)
|
||||
|
|
9
src/groovylight/top.py
Normal file
9
src/groovylight/top.py
Normal file
|
@ -0,0 +1,9 @@
|
|||
# Creates a top-level module based on the display configuration.
|
||||
|
||||
|
||||
from amaranth import Signal
|
||||
from amaranth.lib import wiring, data
|
||||
|
||||
from .hub75
|
||||
|
||||
|
Loading…
Reference in a new issue