format code

This commit is contained in:
Saji 2024-09-27 01:04:17 -05:00
parent bcac3d0dcd
commit ef3df3ae92
7 changed files with 56 additions and 41 deletions

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@ -8,7 +8,6 @@ from amaranth.utils import ceil_log2
from .common import Rgb666Layout, Hub75Stream, Hub75Ctrl, Hub75Data from .common import Rgb666Layout, Hub75Stream, Hub75Ctrl, Hub75Data
class SwapBuffer(wiring.Component): class SwapBuffer(wiring.Component):
"""A pair of BRAMs for holdling line data that are swapped between using an external signal. """A pair of BRAMs for holdling line data that are swapped between using an external signal.

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@ -1,10 +1,8 @@
# main entry point for CLI applications. # main entry point for CLI applications.
import logging import logging
import argparse import argparse
logger = logging.getLogger(__loader__.name) logger = logging.getLogger(__loader__.name)
@ -12,9 +10,7 @@ def setup_logger(args):
root_logger = logging.getLogger() root_logger = logging.getLogger()
handler = logging.StreamHandler() handler = logging.StreamHandler()
formatter = logging.Formatter( formatter = logging.Formatter(style="{", fmt="{levelname:s}: {name:s}: {message:s}")
style="{", fmt="{levelname:s}: {name:s}: {message:s}"
)
handler.setFormatter(formatter) handler.setFormatter(formatter)
root_logger.addHandler(handler) root_logger.addHandler(handler)
@ -33,6 +29,7 @@ def main():
const=logging.DEBUG, const=logging.DEBUG,
default=logging.INFO, default=logging.INFO,
) )
parser.add_argument( parser.add_argument(
"-L", "-L",
"--log-file", "--log-file",

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@ -23,7 +23,9 @@ class Colorlight_5A75B_R82Platform(LatticeECP5Platform):
Subsignal("copi", Pins("T8", dir="o")), Subsignal("copi", Pins("T8", dir="o")),
Attrs(IO_TYPE="LVCMOS33"), Attrs(IO_TYPE="LVCMOS33"),
), ),
*LEDResources(pins="T6", invert=True, attrs=Attrs(IO_TYPE="LVCMOS33", DRIVE="4")), *LEDResources(
pins="T6", invert=True, attrs=Attrs(IO_TYPE="LVCMOS33", DRIVE="4")
),
*ButtonResources( *ButtonResources(
pins="R7", invert=True, attrs=Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP") pins="R7", invert=True, attrs=Attrs(IO_TYPE="LVCMOS33", PULLMODE="UP")
), ),

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@ -13,10 +13,13 @@ from amaranth.lib.wiring import In, Out
# word size = 32 # word size = 32
# 8 megabytes data. # 8 megabytes data.
class SDRAMSignature(wiring.Signature): class SDRAMSignature(wiring.Signature):
""" Signature of a variable-size sdram. Data is split between in/out and has out_en""" """Signature of a variable-size sdram. Data is split between in/out and has out_en"""
def __init__(self, addr_width, data_width=32, bank_width=2): def __init__(self, addr_width, data_width=32, bank_width=2):
super().__init__({ super().__init__(
{
"nCS": Out(1), "nCS": Out(1),
"cke": Out(1), "cke": Out(1),
"nRAS": Out(1), "nRAS": Out(1),
@ -28,31 +31,41 @@ class SDRAMSignature(wiring.Signature):
# todo: use dqm # todo: use dqm
"data_wren": Out(1), "data_wren": Out(1),
"bank_cs": Out(bank_width), "bank_cs": Out(bank_width),
}) }
)
class _WriteBurstLength(enum.Enum, shape=1): class _WriteBurstLength(enum.Enum, shape=1):
"""MRS Write burst mode""" """MRS Write burst mode"""
BURST = 0 BURST = 0
SINGLE_BIT = 1 SINGLE_BIT = 1
class _TestMode(enum.Enum, shape=2): class _TestMode(enum.Enum, shape=2):
""" The "test mode" of the sdram. This is always zero pretty much""" """The "test mode" of the sdram. This is always zero pretty much"""
MODE_REGISTER_SET = 0 MODE_REGISTER_SET = 0
RESERVED0 = 1 RESERVED0 = 1
RESERVED1 = 2 RESERVED1 = 2
RESERVED2 = 3 RESERVED2 = 3
class _CASLatency(enum.Enum, shape=3): class _CASLatency(enum.Enum, shape=3):
""" How many cycles of latency for the column address select to complete """ """How many cycles of latency for the column address select to complete"""
CYCL2 = 2 CYCL2 = 2
CYCL3 = 3 CYCL3 = 3
class _BurstType(enum.Enum, shape=1): class _BurstType(enum.Enum, shape=1):
SEQUENTIAL = 0 SEQUENTIAL = 0
INTERLEAVED = 1 INTERLEAVED = 1
class _BurstLength(enum.IntEnum, shape=3): class _BurstLength(enum.IntEnum, shape=3):
""" The size of the burst """ """The size of the burst"""
SINGLE = 0 SINGLE = 0
DUAL = 1 DUAL = 1
QUAD = 2 QUAD = 2
@ -61,7 +74,8 @@ class _BurstLength(enum.IntEnum, shape=3):
class _Command(enum.Enum): class _Command(enum.Enum):
""" Command set for SDRAM """ """Command set for SDRAM"""
MRS_WRITE = 0 MRS_WRITE = 0
ACTIVATE = 1 ACTIVATE = 1
PRECHARGE = 2 PRECHARGE = 2
@ -73,7 +87,6 @@ class _Command(enum.Enum):
NOP = 8 NOP = 8
class BankController(wiring.Component): class BankController(wiring.Component):
"""Manages a single Bank. Has a bank locking/state tracker, """Manages a single Bank. Has a bank locking/state tracker,
can issue commands""" can issue commands"""

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@ -2,11 +2,12 @@ from ..geom import Coord, BBox
import pytest import pytest
def test_coord_comparison(): def test_coord_comparison():
c1 = Coord(0,0) c1 = Coord(0, 0)
c2 = Coord(0,1) c2 = Coord(0, 1)
c3 = Coord(1,1) c3 = Coord(1, 1)
c3_other = Coord(1,1) c3_other = Coord(1, 1)
assert c1 < c3 assert c1 < c3
assert not c1 < c2, "both x,y must be greater/lt/eq" assert not c1 < c2, "both x,y must be greater/lt/eq"
@ -15,23 +16,24 @@ def test_coord_comparison():
assert c3 == c3_other, "Coords with same numbers should equal each other" assert c3 == c3_other, "Coords with same numbers should equal each other"
assert c3 != c2 assert c3 != c2
def test_coord_construction(): def test_coord_construction():
with pytest.raises(RuntimeError): with pytest.raises(RuntimeError):
Coord(0,-1) Coord(0, -1)
def test_bbox(): def test_bbox():
b = BBox(Coord(1,1), Coord(3,2)) b = BBox(Coord(1, 1), Coord(3, 2))
assert b.width == 2 assert b.width == 2
assert b.height == 1 assert b.height == 1
assert b.contains(Coord(1,2)) assert b.contains(Coord(1, 2))
assert not b.contains(Coord(0,0)) assert not b.contains(Coord(0, 0))
# TODO: test .intersect(other) # TODO: test .intersect(other)
with pytest.raises(RuntimeError): with pytest.raises(RuntimeError):
BBox(Coord(0,0), Coord(1,0)) BBox(Coord(0, 0), Coord(1, 0))
with pytest.raises(RuntimeError): with pytest.raises(RuntimeError):
BBox(Coord(1,1), Coord(0,0)) BBox(Coord(1, 1), Coord(0, 0))

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@ -25,7 +25,9 @@ def test_swapbuffer():
assert ctx.get(dut.read_port.data) == init_color assert ctx.get(dut.read_port.data) == init_color
# swap buffer # swap buffer
ctx.set(dut.selector, 1) ctx.set(dut.selector, 1)
await ctx.tick().repeat(2) # takes two clocks after switching selector to output data. await ctx.tick().repeat(
2
) # takes two clocks after switching selector to output data.
assert ctx.get(dut.read_port.data) == test_color assert ctx.get(dut.read_port.data) == test_color
# TODO: add more assertions/verification # TODO: add more assertions/verification