generated from saji/ecp5-template
cleanup; integrate geom into hub75
This commit is contained in:
parent
ae1ad4633c
commit
dd334e8bad
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@ -19,6 +19,7 @@ logger = logging.getLogger(__name__)
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# FIXME: sizing should be based off of screen size.
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# FIXME: sizing should be based off of screen size.
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CoordLayout = data.StructLayout({"x": unsigned(10), "y": unsigned(10)})
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CoordLayout = data.StructLayout({"x": unsigned(10), "y": unsigned(10)})
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class AddressConverter(wiring.Component):
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class AddressConverter(wiring.Component):
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"""Translates display (x,y) into full screen (x,y) based on geometry"""
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"""Translates display (x,y) into full screen (x,y) based on geometry"""
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@ -103,6 +104,8 @@ class AddressGenerator(wiring.Component):
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def example_rgb_transform(x, y):
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def example_rgb_transform(x, y):
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"""A simple coordinate-RGB transformation that computes RGB values directly from the x-y position
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of the pixel. This is used in the simple case and as a test for the rest of the system."""
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return {
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return {
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"red": x + y,
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"red": x + y,
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"green": x - y,
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"green": x - y,
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@ -162,5 +165,6 @@ class BasicFetcher(wiring.Component):
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def chain_streams(m, streams):
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def chain_streams(m, streams):
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"""For "stream combinators", this allows you to easily chain outputs to inputs."""
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for pair in pairwise(streams):
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for pair in pairwise(streams):
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wiring.connect(m, pair[0].output, pair[1].input)
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wiring.connect(m, pair[0].output, pair[1].input)
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@ -210,6 +210,9 @@ class DisplayGeometry:
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sum += s.dimensions.size
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sum += s.dimensions.size
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return sum
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return sum
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@property
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def strings(self) -> [DisplayString]:
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return self._strings
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def add_string(self, s: DisplayString):
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def add_string(self, s: DisplayString):
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"""Add a new string to the display.
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"""Add a new string to the display.
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@ -3,9 +3,12 @@ from amaranth.build import Platform
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from amaranth.lib import wiring, data
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from amaranth.lib import wiring, data
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from amaranth.lib.wiring import In, Out
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from amaranth.lib.wiring import In, Out
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from amaranth.lib.memory import Memory, ReadPort, WritePort
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from amaranth.lib.memory import Memory, ReadPort, WritePort
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from amaranth_soc import wishbone
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from amaranth.utils import ceil_log2
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from amaranth.utils import ceil_log2
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import logging
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import logging
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from groovylight.geom import DisplayGeometry
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from .common import Rgb666Layout, Hub75Stream, Hub75Ctrl, Hub75Data, Rgb888Layout
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from .common import Rgb666Layout, Hub75Stream, Hub75Ctrl, Hub75Data, Rgb888Layout
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@ -34,10 +37,10 @@ class SwapBuffer(wiring.Component):
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super().__init__(
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super().__init__(
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{
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{
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"selector": In(1),
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"selector": In(1),
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"read_port": In(
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"read_port": Out(
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ReadPort.Signature(addr_width=ceil_log2(depth), shape=shape)
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ReadPort.Signature(addr_width=ceil_log2(depth), shape=shape)
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),
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),
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"write_port": In(
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"write_port": Out(
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WritePort.Signature(addr_width=ceil_log2(depth), shape=shape)
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WritePort.Signature(addr_width=ceil_log2(depth), shape=shape)
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),
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),
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}
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}
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@ -316,11 +319,11 @@ class Hub75DataDriver(wiring.Component):
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class Hub75Coordinator(wiring.Component):
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class Hub75Coordinator(wiring.Component):
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"""A shared-control hub75 driver"""
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"""A shared-control hub75 driver"""
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def __init__(self, n_strings=1):
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def __init__(self, geom: DisplayGeometry):
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self.n_strings = n_strings
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self.geom = geom
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super().__init__(
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super().__init__(
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{
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{
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"hub75": Out(Hub75Ctrl(n_strings)),
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"hub75": Out(Hub75Ctrl(self.geom.n_strings)),
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# TODO: fetching routine? maybe it's passed through.
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# TODO: fetching routine? maybe it's passed through.
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}
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}
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)
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)
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@ -338,33 +341,31 @@ class Hub75Coordinator(wiring.Component):
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startStrings = Signal(1)
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startStrings = Signal(1)
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stringsDone = Signal(1)
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stringsDone = Signal(1)
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for i in range(self.n_strings):
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for idx, string in enumerate(self.geom.strings):
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sb = SwapBuffer(depth=128, shape=data.ArrayLayout(Rgb666Layout, 2))
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sb = SwapBuffer(depth=128, shape=data.ArrayLayout(Rgb888Layout, 2))
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bufs.append(sb)
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bufs.append(sb)
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stringdriver = Hub75DataDriver(
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stringdriver = Hub75DataDriver(
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128, data_shape=Rgb666Layout, double_fetch=False
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string.dimensions.length, data_shape=Rgb888Layout, double_fetch=False
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)
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)
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strings.append(stringdriver)
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strings.append(stringdriver)
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wiring.connect(m, sb.read_port, stringdriver.bram_port)
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wiring.connect(m, sb.read_port, stringdriver.bram)
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# wiring.connect(m, self.hub75.data[idx], stringdriver.data.flip())
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m.d.comb += [
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m.d.comb += [
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self.data[i].eq(stringdriver.display_out),
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self.hub75.data[idx].rgb0.eq(stringdriver.data.rgb0),
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self.hub75.data[idx].rgb1.eq(stringdriver.data.rgb1),
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stringdriver.start.eq(startStrings),
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stringdriver.start.eq(startStrings),
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sb.selector.eq(swapline),
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sb.selector.eq(swapline),
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]
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]
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m.submodules += [sb, stringdriver]
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m.submodules += [sb, stringdriver]
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donearr.append(stringdriver.done)
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donearr.append(stringdriver.done)
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# combine the done signals into one signal with AND-reduction
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# combine the done signals into one signal with AND-reduction
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m.d.comb += stringsDone.eq(Cat(*donearr).all())
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m.d.comb += stringsDone.eq(Cat(*donearr).all())
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self.addr = Signal(5)
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self.addr = Signal(5)
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# handle the fetch side.
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# handle the fetch side.
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# WIP: pass in fetcher/pixgen/geometry.
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# right now we're just going to use a basicFetcher
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# right now we assume that it's just one panel,
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# TODO: support SDRAM framebuffer
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# address is (string_number, hi/lo, addr)
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for i in range(self.n_strings):
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lookup_addr = Cat(i, self.addr, 0)
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# generate a sequence of transfers.
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with m.FSM():
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with m.FSM():
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with m.State("init"):
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with m.State("init"):
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@ -384,131 +385,3 @@ class Hub75Coordinator(wiring.Component):
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# fetch line
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# fetch line
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#
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class Hub75EDriver(wiring.Component):
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"""An optimized driver for hub75 strings.
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This version is faster than most implementations by merging the exposure
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period and the data-write period to happen simultaneously. As a result,
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the display can be brighter due to higher duty cycle.
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NOTICE: this is a direct port of the old verilog code. It isn't up to date with the
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modified structure. Notably, it uses RGB888 with double-fetch (4xclocking)
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"""
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start: In(1)
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done: Out(1)
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out: Out(Hub75Stream())
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buf_addr: Out(9)
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buf_data: In(36)
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row_depth = 128
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bit_depth = 8
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bcm_len = 32
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def elaborate(self, platform: Platform) -> Module:
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m = Module()
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counter = Signal(32)
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bcm_shift: Signal = Signal(4, init=7)
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m.d.sync += counter.eq(counter + 1)
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# construct helper signals.
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ram_r = self.buf_data[16:23]
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ram_b = self.buf_data[8:15]
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ram_g = self.buf_data[0:7]
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ram_rgb_slice = Cat(
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ram_r.bit_select(bcm_shift, 1),
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ram_g.bit_select(bcm_shift, 1),
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ram_b.bit_select(bcm_shift, 1),
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)
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pixnum = Signal(8, reset=127)
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pixrow = Signal(1, reset=0)
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m.d.comb += self.buf_addr.eq(Cat(pixrow, pixnum))
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should_clock = counter < (128 * 2 + 1)
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should_expose = (counter < (32 << (bcm_shift + 1) + 1)).bool() & (
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bcm_shift != 7
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).bool()
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with m.FSM():
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with m.State("init"):
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m.d.sync += [
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bcm_shift.eq(7),
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counter.eq(0),
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self.done.eq(0),
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pixnum.eq(127),
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pixrow.eq(0),
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]
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with m.If(self.start == 1):
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m.next = "prefetch"
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with m.State("prefetch"):
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with m.If(counter == 0):
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m.d.sync += pixrow.eq(0)
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with m.Elif(counter == 1):
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m.d.sync += pixrow.eq(1)
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with m.Elif(counter == 2):
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m.d.sync += self.out.rgb0.eq(ram_rgb_slice)
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with m.Elif(counter == 3):
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m.d.sync += [self.out.rgb1.eq(ram_rgb_slice), counter.eq(0)]
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m.next = "writerow"
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with m.State("writerow"):
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# expose if we haven't done it for long enough yet.
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m.d.sync += self.out.oe.eq(~(should_expose))
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with m.If(should_clock):
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# clock is high on entry
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m.d.sync += self.out.display_clk.eq(counter[1] == 0)
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with m.If(counter[0:1] == 0):
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# rising edge of the clock
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m.d.sync += pixrow.eq(0)
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with m.If(counter[0:1] == 1):
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m.d.sync += [
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pixrow.eq(1),
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self.out.rgb0.eq(ram_rgb_slice),
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]
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with m.If(counter[0:1] == 2):
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m.d.sync += [
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pixnum.eq(pixnum - 1),
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pixrow.eq(0),
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self.out.rgb1.eq(ram_rgb_slice),
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]
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with m.Elif(~(should_expose)):
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# we are done both feeding in the new data and exposing the previous.
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m.d.sync += [counter.eq(0), self.out.display_clk.eq(0)]
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m.next = "latchout"
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with m.State("latchout"):
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m.d.sync += [
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pixnum.eq(127),
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self.out.latch.eq(1),
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]
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with m.If(counter > 3):
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m.d.sync += self.out.latch.eq(0)
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m.d.sync += counter.eq(0)
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with m.If(bcm_shift == 0):
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m.next = "finish"
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with m.Else():
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m.d.sync += bcm_shift.eq(bcm_shift - 1)
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m.next = "prefetch"
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with m.State("finish"):
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m.d.sync += Assert(bcm_shift == 0, "finish without bcm shift 0")
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with m.If(counter < (32)):
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m.d.sync += self.out.oe.eq(0)
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with m.Else():
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m.d.sync += [self.out.oe.eq(1), self.done.eq(1)]
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m.next = "init"
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return m
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if __name__ == "__main__":
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m = Hub75EDriver()
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from amaranth.cli import main
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main(m)
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@ -7,6 +7,7 @@ from random import randrange
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import pytest
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import pytest
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from groovylight.common import Rgb888Layout, Rgb666Layout
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from groovylight.common import Rgb888Layout, Rgb666Layout
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from groovylight.geom import DisplayGeometry, DisplayString, DisplayRotation, DisplayDimensions, Coord
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from groovylight.hub75 import (
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from groovylight.hub75 import (
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DisplayClock,
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DisplayClock,
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@ -146,10 +147,13 @@ def test_datadriver_single(bcm):
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with sim.write_vcd("output.vcd"):
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with sim.write_vcd("output.vcd"):
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sim.run()
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sim.run()
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@pytest.mark.skip()
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def test_hub75_coordinator():
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def test_hub75_coordinator():
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m = Module()
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m = Module()
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m.submodules.dut = dut = Hub75Coordinator(1)
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geom = DisplayGeometry()
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geom.add_string(DisplayString(Coord(0,0), DisplayDimensions(128,64), DisplayRotation.R0))
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geom.add_string(DisplayString(Coord(65,0), DisplayDimensions(128,64), DisplayRotation.R0))
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m.submodules.dut = dut = Hub75Coordinator(geom)
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sim = Simulator(m)
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sim = Simulator(m)
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sim.add_clock(1e-6)
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sim.add_clock(1e-6)
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