From d465fccaed4d61f7772dc6541c20aaaec48700ec Mon Sep 17 00:00:00 2001 From: saji Date: Wed, 22 May 2024 22:26:33 -0500 Subject: [PATCH] wip: refactor and fix rightmost pixel bug hack but now row1 doesn't work. --- sim/inc/devices.hpp | 3 +- sim/inc/tests.hpp | 4 -- sim/src/main.cpp | 136 +++++++++++--------------------------------- verilog/hub75e.sv | 29 +++++----- 4 files changed, 50 insertions(+), 122 deletions(-) diff --git a/sim/inc/devices.hpp b/sim/inc/devices.hpp index 5d3354e..85c31bd 100644 --- a/sim/inc/devices.hpp +++ b/sim/inc/devices.hpp @@ -1,7 +1,7 @@ // Project-specific cosimuluated devices. #pragma once -#include "tests.hpp" #include "Vhub75e.h" +#include "tests.hpp" // slices the RGB values for us. uint8_t rgb_slice(uint32_t rgb, uint8_t bit) { @@ -73,6 +73,7 @@ public: this->xsize = xsize; this->ysize = ysize; row0.clear(); + row1.clear(); prev_oe = out_enable; prev_display_clk = display_clk; prev_latch = latch; diff --git a/sim/inc/tests.hpp b/sim/inc/tests.hpp index 208962e..c902de8 100644 --- a/sim/inc/tests.hpp +++ b/sim/inc/tests.hpp @@ -59,10 +59,6 @@ public: for (int i = 0; i < latency; i++) { addr_lookup_q.push(0); } - - for (int i = 0; i < ram.size(); i++) { - ram[i] = i + 3; - } }; FakeBRAM(int latency, unsigned char &clk, unsigned short &addr_in, diff --git a/sim/src/main.cpp b/sim/src/main.cpp index be0bf13..2a2097d 100644 --- a/sim/src/main.cpp +++ b/sim/src/main.cpp @@ -1,113 +1,12 @@ #include "Vhub75e.h" -#include "tests.hpp" #include "devices.hpp" -#include "verilated.h" -#include "verilated_vcd_c.h" +#include "tests.hpp" #include #include +#include #include -#include #include -void LineDriverTest(VerilatedContext &ctx) { - // create the hub75e driver and run some basic tests - - // we generate 512 random color values (24 bits) - // we load them in. - unsigned long posedge = 0; // counts positive edges. - unsigned long simtime = 0; - auto dut = std::make_unique(&ctx, "dut"); - - VerilatedVcdC *m_trace = new VerilatedVcdC; - dut->trace(m_trace, 5); - - auto bram = FakeBRAM(1, dut->clk, dut->pixbuf_addr, dut->pixbuf_data); - - auto hub75 = HUB75Reciever(128, 64, *dut); - printf("Performing basic test\n"); - bool done = false; - m_trace->open("waveform.vcd"); - - while (!done) { - dut->clk ^= 1; // toggle clock - dut->eval(); - - if (dut->clk == 1) { - // rising edge. - posedge++; - bram.tick(); - } - - dut->write_trig = posedge < 2 ? 1 : 0; - - if (posedge >= 250000) { - done = true; - } - hub75.tick(); - m_trace->dump(simtime); - simtime++; - } - m_trace->close(); -}; - -// int main() { -// auto ctx = std::make_unique(); -// ctx->traceEverOn(true); -// printf("hello world!\n"); -// LineDriverTest(*ctx); -// }; - -TEST_CASE("Hub75 Test") { - auto ctx = std::make_unique(); - // setup DUT - - unsigned long posedge = 0; // counts positive edges. - unsigned long simtime = 0; - auto dut = std::make_unique(ctx.get(), "dut"); - - auto bram = FakeBRAM(1, dut->clk, dut->pixbuf_addr, dut->pixbuf_data); - - auto hub75 = HUB75Reciever(128, 64, *dut); - bool done = false; - - bool driver_done = false; - while (!done) { - dut->clk ^= 1; // toggle clock - dut->eval(); - - if (dut->clk == 1) { - // rising edge. - posedge++; - } - - dut->write_trig = posedge < 2 ? 1 : 0; - if (dut->done) { - done = true; - driver_done = true; - } - - if (posedge >= 250000) { - done = true; - driver_done = false; - } - hub75.tick(); - bram.tick(); - simtime++; - } - REQUIRE(driver_done); - SECTION("Bit Sizing/Count") { - - CHECK(hub75.get_past_rows().size() == 8); - - auto rows = hub75.get_past_rows(); - - for (int i = 0; i < rows.size(); i++) { - auto r = rows[i]; - } - } - SECTION("Pulse width") {} -} - TEST_CASE("HUB75E Driver Test") { auto fixture = VerilatorTestFixture(); // very simple done checker. @@ -122,7 +21,6 @@ TEST_CASE("HUB75E Driver Test") { fixture.add_module(stim); SECTION("Smoke Tests") { - fixture.enable_trace("testing.vcd"); auto bram = std::make_shared(1, dut.clk, dut.pixbuf_addr, dut.pixbuf_data); fixture.add_module(bram); @@ -159,5 +57,35 @@ TEST_CASE("HUB75E Driver Test") { SECTION("Line Correctness") { // this is the part where we validate that the line in = line out. // we have to generate different values since the + fixture.enable_trace("testing.vcd"); + auto line = GENERATE(take(10, chunk(256, random(0, 0xFFFFFF)))); + auto bram = std::make_shared(1, dut.clk, dut.pixbuf_addr, + dut.pixbuf_data); + + std::copy(line.begin(), line.end(), bram->get().begin()); + fixture.add_module(bram); + auto display = std::make_shared(128, 64, dut); + fixture.add_module(display); + + fixture.exec(); + + REQUIRE(fixture.get_reason() == + VerilatorTestFixture::FinishReason::Ok); + + auto [row0, row1] = display->transpose(); + REQUIRE(row0.size() == 128); + REQUIRE(row1.size() == 128); + auto ram_ref = bram->get(); + + for (int i = 0; i < 128; i++) { + CAPTURE(i); + CAPTURE(ram_ref[i], row0[i]); + REQUIRE(ram_ref[i] == row0[i]); + CAPTURE(ram_ref[i+128], row1[i]); + REQUIRE(ram_ref[i+128] == row1[i]); + + } + // CHECK(std::equal(ram_ref.begin(), ram_ref.begin() + 128, row0.begin(), + // row0.end())); } } diff --git a/verilog/hub75e.sv b/verilog/hub75e.sv index c57a82d..ea578f3 100644 --- a/verilog/hub75e.sv +++ b/verilog/hub75e.sv @@ -58,6 +58,9 @@ module hub75e ( reg [7:0] pixnum; + reg pixrow = 0; + + assign pixbuf_addr = {pixrow, pixnum}; always_ff @(posedge clk) begin counter <= counter + 1; @@ -67,7 +70,7 @@ module hub75e ( counter <= 0; done <= 0; pixnum <= ROW_DEPTH - 1; - pixbuf_addr <= {1'b0, pixnum}; + pixrow <= 0; // wait for the signal to write out our lines. if (write_trig) begin state <= StatePreload; @@ -75,19 +78,19 @@ module hub75e ( end StatePreload: begin - case (counter[1:0]) - 2'b00: begin - // wait for pix 1 - pixbuf_addr <= {1'b1, pixnum}; + case (counter) + 0: begin + pixrow <= 0; end - 2'b01: begin + 1: begin // load pix 1 panel_rgb0 <= ram_rgb_slice; + // wait for pix 1 + pixrow <= 1; end - 2'b10: begin // rising edge - // store pix2 + 2: begin panel_rgb1 <= ram_rgb_slice; - // go to writerow + pixrow <= 0; counter <= 0; state <= StateWriteRow; end @@ -104,17 +107,18 @@ module hub75e ( case (counter[1:0]) 2'b10: begin // rising edge // fetch pixel 1 - pixbuf_addr <= {1'b0, pixnum}; + pixrow <= 0; end 2'b11: begin // midpoint of high clk. // fetch pixel 2, load pixel 1 - pixbuf_addr <= {1'b1, pixnum}; + pixrow <= 1; panel_rgb0 <= ram_rgb_slice; end 2'b00: begin // falling edge // load pixel 2 panel_rgb1 <= ram_rgb_slice; pixnum <= pixnum - 1; + pixrow <= 0; end 2'b01: begin // midpoint of low clk // decrement pixnum @@ -143,7 +147,6 @@ module hub75e ( latch <= 1; out_enable <= 1; pixnum <= ROW_DEPTH - 1; - counter <= counter + 1; if (counter > 3) begin counter <= 0; if (bcm_shift == 0) begin @@ -152,7 +155,7 @@ module hub75e ( latch <= 0; end else begin bcm_shift <= bcm_shift - 1; - state <= StateWriteRow; + state <= StatePreload; latch <= 0; end end