generated from saji/ecp5-template
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386403bd12
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@ -70,6 +70,7 @@ class Hub75Data(wiring.Signature):
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}
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)
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class SwapBuffer(wiring.Component):
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"""A pair of BRAMs for holdling line data that are swapped between using an external signal.
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@ -129,7 +130,6 @@ class SwapBuffer(wiring.Component):
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# self.write_port.data.eq(Mux(self.selector, write0.data, write1.data)),
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write0.data.eq(self.write_port.data),
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write1.data.eq(self.write_port.data),
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read0.addr.eq(self.read_port.addr),
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read1.addr.eq(self.read_port.addr),
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read0.en.eq(~self.selector),
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@ -141,63 +141,49 @@ class SwapBuffer(wiring.Component):
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class Hub75StringDriver(wiring.Component):
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"""A data driver for Hub75 panels. This accesses the line memory and feeds out the data"""
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"""A data driver for Hub75 panels. This accesses the line memory and feeds out the data.
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It is controlled by a Hub75Coordinator to signal when it should run and what bit of the data
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it should send.
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"""
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bcm_select: In(3)
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done: Out(1)
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start: In(1)
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active_bank: In(1) # the bank to use
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bram_port: Out(WritePort.Signature(
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addr_width=9, shape=Rgb888Layout
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)) # the other line to be swapped to.
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bram_port: In(ReadPort.Signature(addr_width=9, shape=Rgb888Layout))
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display_out: Out(Hub75Data()) # data signal output.
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def __init__(self, panel_length: int = 128, *, src_loc_at=0):
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self.panel_length = panel_length
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super().__init__(None, src_loc_at=src_loc_at)
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def elaborate(self, platform: Platform) -> Module:
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m = Module()
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# add two memories
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m.submodules.bram0 = bram0 = Memory(shape=Rgb888Layout, depth=512, init=[])
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m.submodules.bram1 = bram1 = Memory(shape=Rgb888Layout, depth=512, init=[])
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# We use two brams here so we can swap between each - that way we can update the data
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# while displaying the other line. Switching is controlled by the coordinator.
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readports = Mux([bram0.read_port(), bram1.read_port()])
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active_readport = readports[self.active_bank]
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m.d.comb += active_readport.eq(readports[self.active_bank])
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writeports = Array([bram0.write_port(), bram1.write_port()])
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m.d.comb += self.bram_port.eq(writeports[~self.active_bank])
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# We want to set up the bram ports
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port0 = bram0.read_port()
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port1 = bram1.read_port()
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# the enable for these ports is based on active bank.
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m.d.comb += port0.en.eq(self.active_bank)
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m.d.comb += port1.en.eq(~self.active_bank)
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counter = Signal(32)
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self._counter = counter = Signal(32)
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m.d.sync += counter.eq(counter + 1)
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ram_rgb_slice = Cat(
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active_readport.data["red"].bit_select(self.bcm_shift, 1),
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active_readport.data["blue"].bit_select(self.bcm_shift, 1),
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active_readport.data["green"].bit_select(self.bcm_shift, 1),
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self.bram_port.data["red"].bit_select(self.bcm_select, 1),
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self.bram_port.data["blue"].bit_select(self.bcm_select, 1),
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self.bram_port.data["green"].bit_select(self.bcm_select, 1),
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)
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pixnum = Signal(8, reset=127)
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pixrow = Signal(1, reset=0)
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m.d.comb += self.buf_addr.eq(Cat(pixrow, pixnum))
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pixnum = Signal(range(self.panel_length), init=self.panel_length - 1)
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pixrow = Signal(1, init=0)
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m.d.comb += self.bram_port.addr.eq(Cat(pixrow, pixnum))
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with m.FSM():
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with m.State("init"):
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m.d.sync += [
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self.done.eq(0),
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counter.eq(0),
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pixnum.eq(127),
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pixnum.eq(self.panel_length - 1),
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pixrow.eq(0),
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]
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with m.If(self.start == 1):
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m.d.sync += active_readport.en.eq(1)
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m.d.sync += self.bram_port.en.eq(1)
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m.next = "prefetch"
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with m.State("prefetch"):
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with m.If(counter == 0):
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@ -209,23 +195,32 @@ class Hub75StringDriver(wiring.Component):
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with m.Elif(counter == 3):
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m.d.sync += [self.display_out.rgb1.eq(ram_rgb_slice), counter.eq(0)]
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m.next = "writerow"
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with m.State("writerow"):
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with m.If(counter[0:1] == 0):
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# rising edge of the clock
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m.d.sync += pixrow.eq(0)
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with m.If(counter[0:1] == 1):
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m.d.sync += [
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pixrow.eq(1),
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self.display_out.rgb0.eq(ram_rgb_slice),
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]
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with m.If(counter[0:1] == 2):
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m.d.sync += [
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pixnum.eq(pixnum - 1),
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pixrow.eq(0),
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self.display_out.rgb1.eq(ram_rgb_slice),
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]
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with m.If(counter == 128 * 2 + 1):
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m.next = "done"
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with m.State("done"):
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m.d.sync += self.done.eq(1)
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m.next = "init"
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return m
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def test_stringdriver():
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dut = Hub75StringDriver()
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sim = Simulator(dut)
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sim.add_clock(1e-6)
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async def testbench(ctx):
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pass
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sim.add_testbench(testbench)
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with sim.write_vcd("output.vcd"):
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sim.run_until(1e-6 * 1000)
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class Hub75Coordinator(wiring.Component):
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"""A shared-control hub75 driver"""
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37
src/groovylight/test_hub75.py
Normal file
37
src/groovylight/test_hub75.py
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@ -0,0 +1,37 @@
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from amaranth import Array, Module, Cat, Signal, Assert, unsigned
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from amaranth.build import Platform
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from amaranth.lib import wiring, data
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from amaranth.lib.wiring import In, Out
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from amaranth.lib.memory import Memory, WritePort
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from amaranth.sim import Simulator
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from .bitslicer import Hub75StringDriver, Rgb888Layout
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def test_stringdriver():
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# the string driver test must
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# 1. finish
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# 2. strobe through all of the data in the array
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# 3. slice the correct bit from the data.
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m = Module()
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m.submodules.dut = dut = Hub75StringDriver()
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m.submodules.mem = mem = Memory(shape=Rgb888Layout, depth=512, init=[])
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port = mem.read_port()
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wiring.connect(m, port, dut.bram_port)
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async def testbench(ctx):
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# select a bit, strobe start, read values, test against known.
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ctx.set(dut.bcm_select, 5)
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ctx.set(dut.start, 1)
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await ctx.tick()
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ctx.set(dut.start, 0)
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assert(ctx.get(dut.bram_port.en) == 1)
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pass
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sim = Simulator(m)
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sim.add_clock(1e-6)
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with sim.write_vcd("output.vcd"):
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sim.run_until(1e-6 * 1000)
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@ -28,6 +28,7 @@ def test_swapbuffer():
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await ctx.tick().repeat(2) # takes two clocks after switching selector to output data.
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assert ctx.get(dut.read_port.data) == test_color
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# TODO: add more assertions/verification
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sim.add_testbench(testbench)
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with sim.write_vcd("output.vcd"):
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sim.run_until(1e-6 * 1000)
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