move things into common
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Verilator Unit Tests / Test (push) Failing after 3m36s

This commit is contained in:
Saji 2024-09-21 14:37:03 -05:00
parent 5820d80db2
commit c601248cf2
3 changed files with 78 additions and 65 deletions

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@ -1,73 +1,12 @@
from amaranth import Module, Cat, Mux, ShapeLike, Signal, Assert, unsigned from amaranth import Module, Cat, Mux, ShapeLike, Signal, Assert
from amaranth.build import Platform from amaranth.build import Platform
from amaranth.lib import wiring, data from amaranth.lib import wiring, data
from amaranth.lib.wiring import In, Out from amaranth.lib.wiring import In, Out
from amaranth.lib.memory import Memory, ReadPort, WritePort from amaranth.lib.memory import Memory, ReadPort, WritePort
from amaranth.utils import ceil_log2 from amaranth.utils import ceil_log2
from .common import Rgb666Layout, Hub75Stream, Hub75Ctrl, Hub75Data
class RGBLayout(data.StructLayout):
def __init__(self, r_bits, g_bits, b_bits):
super().__init__(
{
"red": unsigned(r_bits),
"green": unsigned(g_bits),
"blue": unsigned(b_bits),
}
)
Rgb666Layout = RGBLayout(6, 6, 6)
Rgb111Layout = RGBLayout(1, 1, 1)
class Hub75Stream(wiring.Signature):
"""A Hub75E Driver for a single string of panels."""
def __init__(self):
super().__init__(
{
"latch": Out(1),
"oe": Out(1),
"addr": Out(5),
"rgb0": Out(3),
"rgb1": Out(3),
"display_clk": Out(1),
}
)
class Hub75Ctrl(wiring.Signature):
"""Hub75E control/addressing signals.
This is separated because certain designs keep these common
between all panel outputs (e.g Colorlight 5A-75b boards).
"""
def __init__(self):
super().__init__(
{
"latch": Out(1),
"oe": Out(1),
"addr": Out(5),
"display_clk": Out(1),
}
)
class Hub75Data(wiring.Signature):
"""Data lines for HUB75 displays. When combined with Hub75Ctrl, this forms a complete HUB75 interface.
These are kept separate as some devices have a single set of control signals.
"""
def __init__(self):
super().__init__(
{
"rgb0": Out(Rgb111Layout),
"rgb1": Out(Rgb111Layout),
}
)
class SwapBuffer(wiring.Component): class SwapBuffer(wiring.Component):

67
src/groovylight/common.py Normal file
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@ -0,0 +1,67 @@
from amaranth import unsigned
from amaranth.lib import wiring, data
from amaranth.lib.wiring import Out
class RGBLayout(data.StructLayout):
def __init__(self, r_bits, g_bits, b_bits):
super().__init__(
{
"red": unsigned(r_bits),
"green": unsigned(g_bits),
"blue": unsigned(b_bits),
}
)
Rgb666Layout = RGBLayout(6, 6, 6)
Rgb111Layout = RGBLayout(1, 1, 1)
class Hub75Stream(wiring.Signature):
"""A Hub75E Driver for a single string of panels."""
def __init__(self):
super().__init__(
{
"latch": Out(1),
"oe": Out(1),
"addr": Out(5),
"rgb0": Out(3),
"rgb1": Out(3),
"display_clk": Out(1),
}
)
class Hub75Ctrl(wiring.Signature):
"""Hub75E control/addressing signals.
This is separated because certain designs keep these common
between all panel outputs (e.g Colorlight 5A-75b boards).
"""
def __init__(self):
super().__init__(
{
"latch": Out(1),
"oe": Out(1),
"addr": Out(5),
"display_clk": Out(1),
}
)
class Hub75Data(wiring.Signature):
"""Data lines for HUB75 displays. When combined with Hub75Ctrl, this forms a complete HUB75 interface.
These are kept separate as some devices have a single set of control signals.
"""
def __init__(self):
super().__init__(
{
"rgb0": Out(Rgb111Layout),
"rgb1": Out(Rgb111Layout),
}
)

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@ -156,17 +156,24 @@ class DisplayString:
class DisplayGeometry: class DisplayGeometry:
"""Represents a display based on several strings in different positions.""" """Represents a display based on several strings in different positions."""
_strings: [DisplayString] = []
def __init__(self, *, strict: bool = False): def __init__(self, *, strict: bool = False):
self.strict = strict self.strict = strict
pass pass
def add_string(self, position: (int, int), rot: int, dimensions: (int, int)): def add_string(self, s: DisplayString):
"""Add a new string to the display. This new string is located at """Add a new string to the display. This new string is located at
a specific point, and has a direction, along with dimension that reveal a specific point, and has a direction, along with dimension that reveal
the number of address lines (typically 64, with 1:32 selection so 5 address the number of address lines (typically 64, with 1:32 selection so 5 address
bits) and the total length of the string which is used to size the line bits) and the total length of the string which is used to size the line
buffers. buffers.
When in strict mode, this method may throw an exception if this new string When in strict mode, this method will throw an exception if this new string
will overlap with an existing string. will overlap with an existing string.
""" """
for e in self._strings:
if e.intersects(s):
pass