diff --git a/verilog/bitslicer.sv b/verilog/bitslicer.sv
new file mode 100644
index 0000000..e0342fd
--- /dev/null
+++ b/verilog/bitslicer.sv
@@ -0,0 +1,57 @@
+module bitslicer (
+    input clk,
+    input [23:0] rgb[2],
+    input [7:0] pixnum,  // x-value of the pixels we are being fed.
+    input start_write,
+    output reg [5:0] bitplane_data,
+    output [10:0] bitplane_addr,
+    output reg bitplane_wren,
+    output reg done
+);
+
+  reg [3:0] bitplane_bit = 0;
+  assign bitplane_addr = (pixnum << 3) + bitplane_bit;
+
+  reg [3:0] state = StateInit;
+  localparam integer StateInit = 0;
+  localparam integer StateWriteout = 1;
+  localparam integer StateDone = 2;
+
+
+  always @(posedge clk) begin
+    case (state)
+      StateInit: begin
+        bitplane_bit <= 0;
+        done <= 0;
+        bitplane_wren <= 0;
+        if (start_write) begin
+          state <= StateWriteout;
+        end
+      end
+      StateWriteout: begin
+        bitplane_data <= {
+          rgb[1][bitplane_bit],
+          rgb[1][bitplane_bit+8],
+          rgb[1][bitplane_bit+16],
+          rgb[0][bitplane_bit],
+          rgb[0][bitplane_bit+8],
+          rgb[0][bitplane_bit+16]
+        };
+        bitplane_wren <= 1;
+        bitplane_bit <= bitplane_bit + 1;
+
+        if (bitplane_bit == 7) begin
+          state <= StateDone;
+        end
+      end
+      StateDone: begin
+        bitplane_wren <= 0;
+        done <= 1; // strobe
+        state <= StateInit;
+      end
+      default: begin
+        state <= StateInit;
+      end
+    endcase
+  end
+endmodule
diff --git a/verilog/tb/bitslicer_tb.sv b/verilog/tb/bitslicer_tb.sv
new file mode 100644
index 0000000..e69de29