From b248c4d731907d536fe012aea1c894cdb11c2543 Mon Sep 17 00:00:00 2001 From: saji Date: Fri, 10 May 2024 11:31:51 -0500 Subject: [PATCH] increase speed grade of chip to meet timing for bram --- groovylight/platform/colorlight_5a_75b_8_0.py | 2 +- verilog/lineram.v | 181 +++++++++++------- 2 files changed, 111 insertions(+), 72 deletions(-) diff --git a/groovylight/platform/colorlight_5a_75b_8_0.py b/groovylight/platform/colorlight_5a_75b_8_0.py index 5bab51c..7eb12f4 100644 --- a/groovylight/platform/colorlight_5a_75b_8_0.py +++ b/groovylight/platform/colorlight_5a_75b_8_0.py @@ -124,7 +124,7 @@ class Groovy1Platform(LatticeECP5Platform): default_clk_period = 1e9/25e6 def __init__(self, toolchain='trellis', **kwargs): - self.device = "LFE5U-25F-6BG256C" + self.device = "LFE5U-25F-8BG256C" LatticeECP5Platform.__init__(self, self.device, _io, connectors=_connectors, toolchain=toolchain, **kwargs) def create_programmer(self): diff --git a/verilog/lineram.v b/verilog/lineram.v index cf7921e..d3ca3e0 100644 --- a/verilog/lineram.v +++ b/verilog/lineram.v @@ -1,80 +1,119 @@ -module lineram #( - parameter DATA_WIDTH = 36, - parameter ADDR_WIDTH = 9 -) ( - input [DATA_WIDTH - 1:0] din, - input [ADDR_WIDTH - 1:0] addr_w, - output reg [DATA_WIDTH - 1:0] dout, - input [ADDR_WIDTH - 1:0] addr_r, +module lineram ( + input [35:0] din, + input [8:0] addr_w, + output wire [35:0] dout, + input [8:0] addr_r, input write_en, input read_clk, input write_clk ); - // `ifdef YOSYS - // // use the ECP5 primitive. - // defparam ram.PORT_W_WR_EN_WIDTH = 1; - // $__ECP5_PDPW16KD_ ram ( - // .PORT_R_CLK(read_clk), - // .PORT_R_ADDR(addr_r), - // .PORT_R_RD_DATA(dout), - // .PORT_W_CLK(write_clk), - // .PORT_W_WRITE_EN(write_en), - // .PORT_W_WR_DATA(din), - // ); - // // PDPW16KD ram ( - // // .DI0 (din[0]), - // // .DI1 (din[1]), - // // .DI2 (din[2]), - // // .DI3 (din[3]), - // // .DI4 (din[4]), - // // .DI5 (din[5]), - // // .DI6 (din[6]), - // // .DI7 (din[7]), - // // .DI8 (din[8]), - // // .DI9 (din[9]), - // // .DI10(din[10]), - // // .DI11(din[11]), - // // .DI12(din[12]), - // // .DI13(din[13]), - // // .DI14(din[14]), - // // .DI15(din[15]), - // // .DI16(din[16]), - // // .DI17(din[17]), - // // .DI18(din[18]), - // // .DI19(din[19]), - // // .DI20(din[20]), - // // .DI21(din[21]), - // // .DI22(din[22]), - // // .DI23(din[23]), - // // .DI24(din[24]), - // // .DI25(din[25]), - // // .DI26(din[26]), - // // .DI27(din[27]), - // // .DI28(din[28]), - // // .DI29(din[29]), - // // .DI30(din[30]), - // // .DI31(din[31]), - // // .DI32(din[32]), - // // .DI33(din[33]), - // // .DI34(din[34]), - // // .DI35(din[35]), - // // .ADW0(addr_w[0]), - // // .ADW1(addr_w[1]), - // // .ADW2(addr_w[2]), - // // .ADW3(addr_w[3]), - // // .ADW4(addr_w[4]), - // // .ADW5(addr_w[5]), - // // .ADW6(addr_w[6]), - // // .ADW7(addr_w[7]), - // // .ADW8(addr_w[8]), - // // - // // ); - // `else - reg [DATA_WIDTH - 1:0] ram[2**ADDR_WIDTH]; +// `ifdef YOSYS +// // use the ECP5 primitive. +// PDPW16KD ram ( +// .DI0 (din[0]), +// .DI1 (din[1]), +// .DI2 (din[2]), +// .DI3 (din[3]), +// .DI4 (din[4]), +// .DI5 (din[5]), +// .DI6 (din[6]), +// .DI7 (din[7]), +// .DI8 (din[8]), +// .DI9 (din[9]), +// .DI10(din[10]), +// .DI11(din[11]), +// .DI12(din[12]), +// .DI13(din[13]), +// .DI14(din[14]), +// .DI15(din[15]), +// .DI16(din[16]), +// .DI17(din[17]), +// .DI18(din[18]), +// .DI19(din[19]), +// .DI20(din[20]), +// .DI21(din[21]), +// .DI22(din[22]), +// .DI23(din[23]), +// .DI24(din[24]), +// .DI25(din[25]), +// .DI26(din[26]), +// .DI27(din[27]), +// .DI28(din[28]), +// .DI29(din[29]), +// .DI30(din[30]), +// .DI31(din[31]), +// .DI32(din[32]), +// .DI33(din[33]), +// .DI34(din[34]), +// .DI35(din[35]), +// .ADW0(addr_w[0]), +// .ADW1(addr_w[1]), +// .ADW2(addr_w[2]), +// .ADW3(addr_w[3]), +// .ADW4(addr_w[4]), +// .ADW5(addr_w[5]), +// .ADW6(addr_w[6]), +// .ADW7(addr_w[7]), +// .ADW8(addr_w[8]), +// .DO0 (dout[0]), +// .DO1 (dout[1]), +// .DO2 (dout[2]), +// .DO3 (dout[3]), +// .DO4 (dout[4]), +// .DO5 (dout[5]), +// .DO6 (dout[6]), +// .DO7 (dout[7]), +// .DO8 (dout[8]), +// .DO9 (dout[9]), +// .DO10(dout[10]), +// .DO11(dout[11]), +// .DO12(dout[12]), +// .DO13(dout[13]), +// .DO14(dout[14]), +// .DO15(dout[15]), +// .DO16(dout[16]), +// .DO17(dout[17]), +// .DO18(dout[18]), +// .DO19(dout[19]), +// .DO20(dout[20]), +// .DO21(dout[21]), +// .DO22(dout[22]), +// .DO23(dout[23]), +// .DO24(dout[24]), +// .DO25(dout[25]), +// .DO26(dout[26]), +// .DO27(dout[27]), +// .DO28(dout[28]), +// .DO29(dout[29]), +// .DO30(dout[30]), +// .DO31(dout[31]), +// .DO32(dout[32]), +// .DO33(dout[33]), +// .DO34(dout[34]), +// .DO35(dout[35]), +// .ADR0(addr_r[0]), +// .ADR1(addr_r[1]), +// .ADR2(addr_r[2]), +// .ADR3(addr_r[3]), +// .ADR4(addr_r[4]), +// .ADR5(addr_r[5]), +// .ADR6(addr_r[6]), +// .ADR7(addr_r[7]), +// .ADR8(addr_r[8]), +// .CER(1), +// .CEW(1), +// .CLKR(read_clk), +// .CLKW(write_clk), +// +// +// ); +// `else + reg [35:0] ram [2**9]; + `ifndef YOSYS initial begin - for (int i = 0; i < 2 ** ADDR_WIDTH; i = i + 1) begin + for (integer i = 0; i < 2 ** 9; i = i + 1) begin ram[i] = 0; end end @@ -86,5 +125,5 @@ module lineram #( always @(posedge read_clk) begin dout <= ram[addr_r]; end - // `endif +// `endif endmodule