more things

flake.nix

@@ -47,6 +47,8 @@
             ]))
             yosys
             nextpnr
+            pkgsCross.riscv64.buildPackages.gcc
+            gnumake
             # simulators
             verilog
             verilator

groovylight/platform/colorlight_5a_75b_8_0.py

@@ -91,35 +91,41 @@ _connectors = [
 
 
 class _CRG(LiteXModule):
-    def __init__(self, platform, sys_clk_freq):
+    def __init__(self, platform, sys_clk_freq, with_reset = False):
         self.cd_sys = ClockDomain("sys")
-        self.cd_sdram = ClockDomain("sdram")
+        # self.cd_sdram = ClockDomain("sdram")
+        self.cd_sys2x = ClockDomain()
+        self.cd_sys2x_ps = ClockDomain()
 
         # Clk / Rst.
         clk25 = platform.request("clk25")
-        rst_n = platform.request("user_btn_n", 0)
+
 
         # PLL.
         self.pll = pll = ECP5PLL()
 
-        self.comb = [pll.reset.eq(~rst_n)]
+        rst_n = platform.request("user_btn_n", 0) if with_reset else 1
+        self.comb += [pll.reset.eq(~rst_n)]
         pll.register_clkin(clk25, 25e6)
         pll.create_clkout(self.cd_sys, sys_clk_freq)
         # for the sdram
-        pll.create_clkout(self.cd_sdram, sys_clk_freq, phase=180)
+        # pll.create_clkout(self.cd_sdram, sys_clk_freq, phase=180)
+        pll.create_clkout(self.cd_sys2x,    2*sys_clk_freq)
+        pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) 
 
 
-        sdram_clk = ClockSignal("sdram")
+        sdram_clk = ClockSignal("sys2x_ps")
-        self.specials = DDROutput(1,0, platform.request("sdram_clock"), sdram_clk)
+        # sdram_clk = ClockSignal("sdram")
+        self.specials += DDROutput(1,0, platform.request("sdram_clock"), sdram_clk)
 
 
-class Platform(LatticeECP5Platform):
+class Groovy1Platform(LatticeECP5Platform):
     default_clk_name = "clk25"
     default_clk_period = 1e9/25e6
 
     def __init__(self, toolchain='trellis', **kwargs):
-        device = "LFE5U-25F-6BG256C"
+        self.device = "LFE5U-25F-6BG256C"
-        LatticeECP5Platform.__init__(self, device, _io, connectors=_connectors, toolchain=toolchain)
+        LatticeECP5Platform.__init__(self, self.device, _io, connectors=_connectors, toolchain=toolchain, **kwargs)
 
     def create_programmer(self):
         return OpenFPGALoader(cable="cmsisdap")
@@ -129,7 +135,7 @@ class Platform(LatticeECP5Platform):
         return crg
 
     def do_finalize(self, fragment, *args, **kwargs):
-        LatticeECP5Platform.do_finalize(self, fragment)
+        LatticeECP5Platform.do_finalize(self, fragment, *args, **kwargs)
         self.add_period_constraint(self.lookup_request("clk25",            loose=True), 1e9/25e6)
         self.add_period_constraint(self.lookup_request("eth_clocks:rx", 0, loose=True), 1e9/125e6)
         self.add_period_constraint(self.lookup_request("eth_clocks:rx", 1, loose=True), 1e9/125e6)

groovylight/soc.py

@@ -4,18 +4,76 @@ from litex.gen import LiteXModule, ClockDomain, ClockSignal
 
 from litex.soc.cores.cpu import vexriscv
 from litex.soc.integration.soc_core import SoCCore
-from litex.soc.integration.builder import Builder
+from litex.soc.integration.builder import Builder, builder_argdict, builder_args
+from litex.soc.integration.soc_core import soc_core_argdict, soc_core_args
+from litex.build.lattice.trellis import trellis_argdict, trellis_args
 
 from litedram.modules import M12L64322A
+from litedram.phy import GENSDRPHY, HalfRateGENSDRPHY
 from liteeth.phy.ecp5rgmii import LiteEthPHYRGMII
 
-
+from platform.colorlight_5a_75b_8_0 import Groovy1Platform
 
 
 class GroovySoC(SoCCore):
-    def __init__(self, platform, sys_clk_freq, **kwargs):
+    def __init__(self, platform, sys_clk_freq,
+                 use_spi = False,
+                 **kwargs):
+
         SoCCore.__init__(self, platform, sys_clk_freq, ident="LiteX SoC for GroovyLight", **kwargs)
 
+
         self.crg = platform.get_crg(sys_clk_freq)
         self.submodules += self.crg
+        print(kwargs)
 
+        if not self.integrated_main_ram_size:
+            self.sdrphy = HalfRateGENSDRPHY(platform.request("sdram"), sys_clk_freq)
+            self.add_sdram("sdram",
+                phy                     = self.sdrphy,
+                module                  = M12L64322A(sys_clk_freq, "1:2"),
+                l2_cache_size           = kwargs.get("l2_size", 8192),
+            )
+
+
+        self.submodules.ethphy = LiteEthPHYRGMII(
+                clock_pads= self.platform.request("eth_clocks", 0),
+                pads = self.platform.request("eth", 0),
+                tx_delay = 0e-9, # not sure what this is
+                )
+        self.add_csr("ethphy")
+        self.add_etherbone(phy=self.ethphy, ip_address="192.168.0.36", mac_address = 0x10e2d5000001, data_width=32)
+        if use_spi:
+            from litespi.modules import W25Q32JV as SpiFlashModule
+            from litespi.opcodes import SpiNorFlashOpCodes
+            self.mem_map["spiflash"] = 0x20000000
+            mod = SpiFlashModule(SpiNorFlashOpCodes.READ_1_1_1)
+            self.add_spi_flash(mode="1x", module=SpiFlashModule, with_master=False)
+
+
+
+
+import argparse
+
+def main():
+    parser = argparse.ArgumentParser(description="Groovylight builder")
+
+    builder_arggroup = parser.add_argument_group("builder options")
+    soc_arggroup = parser.add_argument_group('SoC core options')
+    soc_arggroup.add_argument("--with-spiflash", action="store_true", help="Use built in SPI flash")
+
+    builder_args(builder_arggroup)
+    soc_core_args(soc_arggroup)
+    trellis_args(parser.add_argument_group('Trellis options'))
+    args = parser.parse_args()
+    platform = Groovy1Platform()
+    soc = GroovySoC(platform, 75e6, **soc_core_argdict(args))
+
+
+    builder = Builder(soc, **builder_argdict(args))
+
+    builder.build()
+
+
+if __name__ == "__main__":
+    main()

litex/pythondata-software-picolibc.nix

@@ -9,7 +9,8 @@ tag: {
     owner = "litex-hub";
     repo = "pythondata-software-picolibc";
     rev = "${tag}";
-    hash = "sha256-5OY17BA37c6aHOvUwb0gJwXxGey4TdUiTTxJD5wuSGU=";
+    fetchSubmodules = true;
+    hash = "sha256-0OpEdBGu/tkFFPUi1RLsTqF2tKwLSfYIi+vPqgfLMd8=";
   };
 
   doCheck = false;