diff --git a/groovylight/hub75.py b/groovylight/hub75.py
index 64c62c3..c06ceff 100644
--- a/groovylight/hub75.py
+++ b/groovylight/hub75.py
@@ -4,6 +4,7 @@
 from litex.build.generic_platform import Signal, Subsignal, Pins
 from litex.build.io import FSM, Module
 from litex.gen import If, NextState, NextValue
+from migen import Cat
 
 def make_hub75_iodevice(index, basename):
     b = basename
@@ -31,63 +32,90 @@ class Hub75Driver(Module):
         self.addr = Signal(5)
         self.latch = Signal()
         self.output_en = Signal()
-        self.rgb = Signal(6)
+        self.rgb = Signal(6, reset=0b111010)
 
 
         # clk-en acts as a gate.
         clock_en = Signal()
         
         self.clock_out = Signal()
-        # self.comb += self.clock_out.eq(self.phase & clock_en)
-        # clock counter increments.
-        self.sync += self.phase.eq(self.phase + 1)
-
-        # self.sync += If(self.phase == 1, If(clock_en, self.clock_out.eq(self.phase)).Else(self.clock_out.eq(0)))
-        self.sync += If(clock_en, self.clock_out.eq(self.phase)).Else(self.clock_out.eq(0))
 
         self.fsm = fsm = FSM()
         self.submodules += self.fsm
+        bcm_value = Signal(3)
 
-        self.comb += self.rgb.eq(0b111010)
+        counter = Signal(32)
 
-        counter = Signal(8)
-
-        fsm.act("ready",
-                NextValue(self.output_en, 1),
-                NextValue(self.pixnum, linedepth - 1),
-                NextValue(self.latch, 0),
-                If(self.phase == 1,
-                   NextValue(self.addr, self.addr + 1),
-                   NextValue(clock_en, 1),
-                   NextState("transmit"),
+        fsm.act("WRITEROW",
+                self.output_en.eq(1),
+                If(counter < 256,
+                    self.clock_out.eq(counter[0]),
+                    NextValue(counter, counter + 1),
+                    If(counter[0], NextValue(self.rgb, self.rgb + 3)),
+                ).Else(
+                    NextValue(counter, 0),
+                    NextState("EXPOSE"),
                 ),
-                # If((self.state_count == 7), NextValue(clock_en, ~clock_en)),
-        )
-        fsm.act("transmit",
-            If(self.phase == 1,
-                NextValue(self.pixnum, self.pixnum - 1),
-                If(self.pixnum == 0,
-                   NextState("latch_delay"),
-                )
-            )
-        )
-        fsm.act("latch_delay",
-            NextValue(clock_en, 0),
-                If(self.phase == 1,
-                   NextState("latchout")
-                   )
-                )
-        fsm.act("latchout",
-            If(self.phase == 1,
-               NextValue(self.latch, 1),
-               NextValue(counter, 0),
-               NextState("done")
-            )
-        )
-        fsm.act("done",
-            NextValue(self.output_en, 0),
-            NextValue(self.latch, 0),
-            NextValue(counter, counter + 1),
-            If(counter == 255, NextState("ready"))
         )
 
+        fsm.act("EXPOSE",
+                self.output_en.eq(0),
+                If(counter < (1000 << bcm_value),
+                   NextValue(counter, counter + 1),
+                ).Else(
+                    NextValue(counter, 0),
+                    NextState("LATCH"),
+                ),
+        )
+
+        fsm.act("LATCH",
+                self.latch.eq(1),
+                NextValue(counter, 0),
+                If(bcm_value == 7,
+                    NextValue(bcm_value, 0),
+                    NextValue(self.addr, self.addr + 1),
+                ).Else(NextValue(bcm_value, 1)),
+                
+                NextState("WRITEROW"),
+        )
+
+
+        # fsm.act("ready",
+        #         NextValue(self.output_en, 1),
+        #         NextValue(self.pixnum, linedepth - 1),
+        #         NextValue(self.latch, 0),
+        #         If(self.phase == 1,
+        #            NextValue(self.addr, self.addr + 1),
+        #            NextValue(clock_en, 1),
+        #            NextState("transmit"),
+        #         ),
+        #         # If((self.state_count == 7), NextValue(clock_en, ~clock_en)),
+        # )
+        # fsm.act("transmit",
+        #     If(self.phase == 1,
+        #         NextValue(self.pixnum, self.pixnum - 1),
+        #         If(self.pixnum == 0,
+        #            NextState("latch_delay"),
+        #         )
+        #     )
+        # )
+        # fsm.act("latch_delay",
+        #     NextValue(clock_en, 0),
+        #         If(self.phase == 1,
+        #            NextState("latchout")
+        #            )
+        #         )
+        # fsm.act("latchout",
+        #     If(self.phase == 1,
+        #        NextValue(self.latch, 1),
+        #        NextValue(counter, 0),
+        #        NextState("done")
+        #     )
+        # )
+        # fsm.act("done",
+        #     NextValue(self.output_en, 0),
+        #     NextValue(self.latch, 0),
+        #     NextValue(counter, counter + 1),
+        #     If(counter == 255, NextState("ready"))
+        # )
+        #
diff --git a/groovylight/platform/colorlight_5a_75b_8_0.py b/groovylight/platform/colorlight_5a_75b_8_0.py
index e8874c9..1afab65 100644
--- a/groovylight/platform/colorlight_5a_75b_8_0.py
+++ b/groovylight/platform/colorlight_5a_75b_8_0.py
@@ -113,7 +113,7 @@ class _CRG(LiteXModule):
         # pll.create_clkout(self.cd_sdram, sys_clk_freq, phase=180)
         pll.create_clkout(self.cd_sys2x,    2*sys_clk_freq)
         pll.create_clkout(self.cd_sys2x_ps, 2*sys_clk_freq, phase=180) 
-        pll.create_clkout(self.cd_hub, 30e6)
+        pll.create_clkout(self.cd_hub, 60e6)
 
 
         sdram_clk = ClockSignal("sys2x_ps")
diff --git a/groovylight/soc.py b/groovylight/soc.py
index dd3ad0a..d39bd07 100644
--- a/groovylight/soc.py
+++ b/groovylight/soc.py
@@ -49,7 +49,7 @@ class GroovySoC(SoCCore):
             self.mem_map["spiflash"] = 0x20000000
             mod = SpiFlashModule(SpiNorFlashOpCodes.READ_1_1_1)
             self.add_spi_flash(mode="1x", module=SpiFlashModule, with_master=False)
-        self.platform.add_extension(make_hub75_iodevice(0, "j4"))
+        self.platform.add_extension(make_hub75_iodevice(0, "j8"))
         hub_io = self.platform.request("hub75_iodev", 0)
         self.submodules.hub75 = hub75 = ClockDomainsRenamer("hub")(Hub75Driver())
         self.comb += [