From 83546779083c2c037b7aa20e1576c1c41aeca828 Mon Sep 17 00:00:00 2001 From: saji <9110284+kschamplin@users.noreply.github.com> Date: Sat, 25 May 2024 12:16:18 -0500 Subject: [PATCH] fix ci --- .gitea/workflows/test.yaml | 2 +- sim/src/main.cpp | 86 +------------------------------------- 2 files changed, 3 insertions(+), 85 deletions(-) diff --git a/.gitea/workflows/test.yaml b/.gitea/workflows/test.yaml index 0a4683c..608aec3 100644 --- a/.gitea/workflows/test.yaml +++ b/.gitea/workflows/test.yaml @@ -18,5 +18,5 @@ jobs: cmake --build build/ working-directory: ./sim - name: Run Simulator - run: ./build/sim + run: ./build/sim_test working-directory: ./sim diff --git a/sim/src/main.cpp b/sim/src/main.cpp index 3fda243..9a77b6e 100644 --- a/sim/src/main.cpp +++ b/sim/src/main.cpp @@ -1,87 +1,5 @@ -#include "Vhub75e.h" -#include "devices.hpp" -#include "tests.hpp" -#include -#include -#include -#include -#include - -TEST_CASE("HUB75E Driver Test") { - auto fixture = VerilatorTestFixture(); - // very simple done checker. - auto done_check = [](Vhub75e &dut, unsigned long time) { - return dut.done == 1; - }; - fixture.set_done_callback(done_check); - const Vhub75e &dut = fixture.get(); - // stimulus to start the transaction. - auto stim = std::make_shared(dut.write_trig, 4); - fixture.add_module(stim); - fixture.set_timeout(250000); - auto bram = std::make_shared(1, dut.clk, dut.pixbuf_addr, - dut.pixbuf_data); - fixture.add_module(bram); - auto display = std::make_shared(128, 64, dut); - fixture.add_module(display); +#include "util/sokol_imgui.h" - SECTION("Smoke Tests") { - - fixture.exec(); - - CHECK(fixture.get_reason() == - VerilatorTestFixture::FinishReason::Ok); - - auto rows = display->get_past_rows(); - CHECK(rows.size() == 8); - for (int i = 0; i < rows.size(); i++) { - auto &[r0, r1] = rows[i]; - CHECK(r0.size() == 128); - CHECK(r1.size() == 128); - } - // pulse width smoke tests. - auto pulses = display->get_pulse_widths(); - REQUIRE(pulses.size() == rows.size()); - for (int i = 1; i < pulses.size(); i++) { - REQUIRE(pulses[i] == pulses[i - 1] / 2); - } - auto [row0, row1] = display->transpose(); - REQUIRE(row0.size() == 128); - REQUIRE(row1.size() == 128); - auto ram_ref = bram->get(); - - CAPTURE(row0); - CHECK(std::equal(ram_ref.begin(), ram_ref.begin() + 128, row0.begin(), - row0.end())); - } - SECTION("Line Correctness") { - // this is the part where we validate that the line in = line out. - // we have to generate different values since the - fixture.enable_trace("testing.vcd"); - // generate an entire block of RAM - auto line = GENERATE(take(1, chunk(512, random(0, 0xFFFFFF)))); - std::copy(line.begin(), line.end(), bram->get().begin()); - - fixture.exec(); - - REQUIRE(fixture.get_reason() == - VerilatorTestFixture::FinishReason::Ok); - - auto [row0, row1] = display->transpose(); - REQUIRE(row0.size() == 128); - REQUIRE(row1.size() == 128); - auto ram_ref = bram->get(); - - for (int i = 0; i < 128; i++) { - CAPTURE(i); - CAPTURE(ram_ref[i], row0[i]); - CHECK(ram_ref[i] == row0[i]); - CAPTURE(ram_ref[i+256], row1[i]); - CHECK(ram_ref[i+256] == row1[i]); - - } - // CHECK(std::equal(ram_ref.begin(), ram_ref.begin() + 128, row0.begin(), - // row0.end())); - } +int main() { }