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fix bram behavior, adjust row offset
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Verilator Unit Tests / Test (push) Failing after 8m15s
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saji 2024-05-23 00:34:26 -05:00
parent 32deb30c92
commit 7cd0e1c53c
2 changed files with 15 additions and 16 deletions
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25
sim/inc/tests.hpp
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@ -4,15 +4,14 @@
#include "verilated.h" #include "verilated.h"
#include "verilated_vcd_c.h" #include "verilated_vcd_c.h"
#include <cstdint> #include <cstdint>
#include <span>
#include <memory> #include <memory>
#include <queue> #include <queue>
#include <span>
#include <vector> #include <vector>
// represents a generic co-simulated device. // represents a generic co-simulated device.
// While this abstract class is very simple, it enables dynamic behavior to be added to the // While this abstract class is very simple, it enables dynamic behavior to be
// simulation fixture. // added to the simulation fixture.
class CosimulatedDevice { class CosimulatedDevice {
public: public:
virtual ~CosimulatedDevice(){}; virtual ~CosimulatedDevice(){};
@ -20,7 +19,6 @@ public:
virtual void tick() = 0; virtual void tick() = 0;
}; };
// Simple stimulus class used to trigger basic operations // Simple stimulus class used to trigger basic operations
class PulseStimulus : public CosimulatedDevice { class PulseStimulus : public CosimulatedDevice {
unsigned long width; unsigned long width;
@ -51,6 +49,7 @@ class FakeBRAM : public CosimulatedDevice {
unsigned long &data_out; unsigned long &data_out;
unsigned char &clk; unsigned char &clk;
unsigned char prev_clk;
public: public:
FakeBRAM(int latency, unsigned char &clk, unsigned short &addr_in, FakeBRAM(int latency, unsigned char &clk, unsigned short &addr_in,
@ -68,16 +67,20 @@ public:
for (int i = 0; i < latency; i++) { for (int i = 0; i < latency; i++) {
addr_lookup_q.push(0); addr_lookup_q.push(0);
} }
prev_clk = clk;
} }
void tick() { void tick() {
// we push and pop in the same tick: this way we keep the queue the same // we push and pop in the same tick: this way we keep the queue the same
// size, acting as a pipeline delay. // size, acting as a pipeline delay.
addr_lookup_q.push(addr_in); if (prev_clk == 0 && clk == 1) { // rising edge
addr_lookup_q.push(addr_in);
auto addr_to_load = addr_lookup_q.front(); auto addr_to_load = addr_lookup_q.front();
addr_lookup_q.pop(); addr_lookup_q.pop();
data_out = ram.at(addr_to_load); data_out = ram.at(addr_to_load);
}
prev_clk = clk;
} }
// TODO: allow accessing/setting the data // TODO: allow accessing/setting the data
@ -86,14 +89,10 @@ public:
void write(unsigned short addr, unsigned long data) { ram[addr] = data; } void write(unsigned short addr, unsigned long data) { ram[addr] = data; }
}; };
// test fixture to reduce amount of runtime code. // test fixture to reduce amount of runtime code.
// Supports: // Supports:
// adding external modules // adding external modules
// running the test // running the test
// storing if the done flag was raised (or not)
//
// TODO: tracing.
template <typename DUT> class VerilatorTestFixture { template <typename DUT> class VerilatorTestFixture {
public: public:
enum class FinishReason { Ok, Timeout }; enum class FinishReason { Ok, Timeout };

6
sim/src/main.cpp
View file

@ -58,7 +58,7 @@ TEST_CASE("HUB75E Driver Test") {
// this is the part where we validate that the line in = line out. // this is the part where we validate that the line in = line out.
// we have to generate different values since the // we have to generate different values since the
fixture.enable_trace("testing.vcd"); fixture.enable_trace("testing.vcd");
auto line = GENERATE(take(10, chunk(256, random(0, 0xFFFFFF)))); auto line = GENERATE(take(10, chunk(512, random(0, 0xFFFFFF))));
auto bram = std::make_shared<FakeBRAM>(1, dut.clk, dut.pixbuf_addr, auto bram = std::make_shared<FakeBRAM>(1, dut.clk, dut.pixbuf_addr,
dut.pixbuf_data); dut.pixbuf_data);
@ -81,8 +81,8 @@ TEST_CASE("HUB75E Driver Test") {
CAPTURE(i); CAPTURE(i);
CAPTURE(ram_ref[i], row0[i]); CAPTURE(ram_ref[i], row0[i]);
REQUIRE(ram_ref[i] == row0[i]); REQUIRE(ram_ref[i] == row0[i]);
CAPTURE(ram_ref[i+128], row1[i]); CAPTURE(ram_ref[i+256], row1[i]);
REQUIRE(ram_ref[i+128] == row1[i]); REQUIRE(ram_ref[i+256] == row1[i]);
} }
// CHECK(std::equal(ram_ref.begin(), ram_ref.begin() + 128, row0.begin(), // CHECK(std::equal(ram_ref.begin(), ram_ref.begin() + 128, row0.begin(),