diff --git a/sim/CMakeLists.txt b/sim/CMakeLists.txt index 1292ca8..139df46 100644 --- a/sim/CMakeLists.txt +++ b/sim/CMakeLists.txt @@ -88,6 +88,7 @@ target_link_libraries(sim PUBLIC imgui) + # SIM TEST add_executable(sim_test) target_sources(sim_test PRIVATE diff --git a/src/groovylight/sdram.py b/src/groovylight/sdram.py index e00a4ce..29b6c0b 100644 --- a/src/groovylight/sdram.py +++ b/src/groovylight/sdram.py @@ -13,20 +13,25 @@ from amaranth.lib.wiring import In, Out # word size = 32 # 8 megabytes data. - -sdram_control_layout = data.StructLayout( - { - "nCS": 1, - "nRAS": 1, - "nCAS": 1, - "nWE": 1, - } -) - - +class SDRAMSignature(wiring.Signature): + """ Signature of a variable-size sdram. Data is split between in/out and has out_en""" + def __init__(self, addr_width, data_width=32, bank_width=2): + super().__init__({ + "nCS": Out(1), + "cke": Out(1), + "nRAS": Out(1), + "nCAS": Out(1), + "nWE": Out(1), + "addr": Out(addr_width), + "data_out": Out(data_width), + "data_in": In(data_width), + # todo: use dqm + "data_wren": Out(1), + "bank_cs": Out(bank_width), + }) class _WriteBurstLength(enum.Enum, shape=1): - """MRS field""" + """MRS Write burst mode""" BURST = 0 SINGLE_BIT = 1 @@ -52,7 +57,7 @@ class _BurstLength(enum.IntEnum, shape=3): DUAL = 1 QUAD = 2 OCT = 3 - FULL_PAGE = 7 + FULL_PAGE = 7 # this is 256 words? class _Command(enum.Enum): @@ -68,3 +73,7 @@ class _Command(enum.Enum): NOP = 8 + +class BankController(wiring.Component): + """Manages a single Bank. Has a bank locking/state tracker, + can issue commands""" diff --git a/verilog/coordinator.sv b/verilog/coordinator.sv index b6b1232..39ea7d3 100644 --- a/verilog/coordinator.sv +++ b/verilog/coordinator.sv @@ -58,7 +58,7 @@ module coordinator ( ); // driver - reg write_line; + reg write_line; wire line_done; hub75e driver ( @@ -113,10 +113,10 @@ module coordinator ( end end StateShowLine: begin - write_line <= 0; - if (line_done) begin - state <= StateIncrementLine; - end + write_line <= 0; + if (line_done) begin + state <= StateIncrementLine; + end end StateIncrementLine: begin x <= 0; diff --git a/verilog/lineram.v b/verilog/lineram.v index 5f97d91..7c8bf21 100644 --- a/verilog/lineram.v +++ b/verilog/lineram.v @@ -8,116 +8,114 @@ module lineram ( input write_clk ); - `ifdef YOSYS - // use the ECP5 primitive. - PDPW16KD #(.REGMODE("OUTREG")) ram ( - .DI0 (din[0]), - .DI1 (din[1]), - .DI2 (din[2]), - .DI3 (din[3]), - .DI4 (din[4]), - .DI5 (din[5]), - .DI6 (din[6]), - .DI7 (din[7]), - .DI8 (din[8]), - .DI9 (din[9]), - .DI10(din[10]), - .DI11(din[11]), - .DI12(din[12]), - .DI13(din[13]), - .DI14(din[14]), - .DI15(din[15]), - .DI16(din[16]), - .DI17(din[17]), - .DI18(din[18]), - .DI19(din[19]), - .DI20(din[20]), - .DI21(din[21]), - .DI22(din[22]), - .DI23(din[23]), - .DI24(din[24]), - .DI25(din[25]), - .DI26(din[26]), - .DI27(din[27]), - .DI28(din[28]), - .DI29(din[29]), - .DI30(din[30]), - .DI31(din[31]), - .DI32(din[32]), - .DI33(din[33]), - .DI34(din[34]), - .DI35(din[35]), - .ADW0(addr_w[0]), - .ADW1(addr_w[1]), - .ADW2(addr_w[2]), - .ADW3(addr_w[3]), - .ADW4(addr_w[4]), - .ADW5(addr_w[5]), - .ADW6(addr_w[6]), - .ADW7(addr_w[7]), - .ADW8(addr_w[8]), - .DO0 (dout[0]), - .DO1 (dout[1]), - .DO2 (dout[2]), - .DO3 (dout[3]), - .DO4 (dout[4]), - .DO5 (dout[5]), - .DO6 (dout[6]), - .DO7 (dout[7]), - .DO8 (dout[8]), - .DO9 (dout[9]), - .DO10(dout[10]), - .DO11(dout[11]), - .DO12(dout[12]), - .DO13(dout[13]), - .DO14(dout[14]), - .DO15(dout[15]), - .DO16(dout[16]), - .DO17(dout[17]), - .DO18(dout[18]), - .DO19(dout[19]), - .DO20(dout[20]), - .DO21(dout[21]), - .DO22(dout[22]), - .DO23(dout[23]), - .DO24(dout[24]), - .DO25(dout[25]), - .DO26(dout[26]), - .DO27(dout[27]), - .DO28(dout[28]), - .DO29(dout[29]), - .DO30(dout[30]), - .DO31(dout[31]), - .DO32(dout[32]), - .DO33(dout[33]), - .DO34(dout[34]), - .DO35(dout[35]), - .ADR0(addr_r[0]), - .ADR1(addr_r[1]), - .ADR2(addr_r[2]), - .ADR3(addr_r[3]), - .ADR4(addr_r[4]), - .ADR5(addr_r[5]), - .ADR6(addr_r[6]), - .ADR7(addr_r[7]), - .ADR8(addr_r[8]), - .CER(1), - .CEW(1), - .CLKR(read_clk), - .CLKW(write_clk), - .CSW1(0), - .CSW2(0), - .CSW3(0), - .CSR1(0), - .CSR2(0), - .CSR3(0), - ); -`else - reg [35:0] ram [2**9]/*verilator public*/; +// `ifdef YOSYS +// // use the ECP5 primitive. +// PDPW16KD #(.REGMODE("OUTREG")) ram ( +// .DI0 (din[0]), +// .DI1 (din[1]), +// .DI2 (din[2]), +// .DI3 (din[3]), +// .DI4 (din[4]), +// .DI5 (din[5]), +// .DI6 (din[6]), +// .DI7 (din[7]), +// .DI8 (din[8]), +// .DI9 (din[9]), +// .DI10(din[10]), +// .DI11(din[11]), +// .DI12(din[12]), +// .DI13(din[13]), +// .DI14(din[14]), +// .DI15(din[15]), +// .DI16(din[16]), +// .DI17(din[17]), +// .DI18(din[18]), +// .DI19(din[19]), +// .DI20(din[20]), +// .DI21(din[21]), +// .DI22(din[22]), +// .DI23(din[23]), +// .DI24(din[24]), +// .DI25(din[25]), +// .DI26(din[26]), +// .DI27(din[27]), +// .DI28(din[28]), +// .DI29(din[29]), +// .DI30(din[30]), +// .DI31(din[31]), +// .DI32(din[32]), +// .DI33(din[33]), +// .DI34(din[34]), +// .DI35(din[35]), +// .ADW0(addr_w[0]), +// .ADW1(addr_w[1]), +// .ADW2(addr_w[2]), +// .ADW3(addr_w[3]), +// .ADW4(addr_w[4]), +// .ADW5(addr_w[5]), +// .ADW6(addr_w[6]), +// .ADW7(addr_w[7]), +// .ADW8(addr_w[8]), +// .DO0 (dout[0]), +// .DO1 (dout[1]), +// .DO2 (dout[2]), +// .DO3 (dout[3]), +// .DO4 (dout[4]), +// .DO5 (dout[5]), +// .DO6 (dout[6]), +// .DO7 (dout[7]), +// .DO8 (dout[8]), +// .DO9 (dout[9]), +// .DO10(dout[10]), +// .DO11(dout[11]), +// .DO12(dout[12]), +// .DO13(dout[13]), +// .DO14(dout[14]), +// .DO15(dout[15]), +// .DO16(dout[16]), +// .DO17(dout[17]), +// .DO18(dout[18]), +// .DO19(dout[19]), +// .DO20(dout[20]), +// .DO21(dout[21]), +// .DO22(dout[22]), +// .DO23(dout[23]), +// .DO24(dout[24]), +// .DO25(dout[25]), +// .DO26(dout[26]), +// .DO27(dout[27]), +// .DO28(dout[28]), +// .DO29(dout[29]), +// .DO30(dout[30]), +// .DO31(dout[31]), +// .DO32(dout[32]), +// .DO33(dout[33]), +// .DO34(dout[34]), +// .DO35(dout[35]), +// .ADR0(addr_r[0]), +// .ADR1(addr_r[1]), +// .ADR2(addr_r[2]), +// .ADR3(addr_r[3]), +// .ADR4(addr_r[4]), +// .ADR5(addr_r[5]), +// .ADR6(addr_r[6]), +// .ADR7(addr_r[7]), +// .ADR8(addr_r[8]), +// .CER(1), +// .CEW(1), +// .CLKR(read_clk), +// .CLKW(write_clk), +// .CSW1(0), +// .CSW2(0), +// .CSR1(0), +// .CSR2(0), +// ); +// `else + reg [35:0] ram [512]/*verilator public*/; `ifndef YOSYS initial begin - for (integer i = 0; i < 2 ** 9; i = i + 1) begin + for (integer i = 0; i < 512; i = i + 1) begin ram[i] = 0; end end @@ -129,5 +127,5 @@ module lineram ( always @(posedge read_clk) begin dout <= ram[addr_r]; end -`endif +// `endif endmodule