generated from saji/ecp5-template
add more tests to display data driver
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Unit Tests / Test (push) Successful in 2m25s
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Unit Tests / Test (push) Successful in 2m25s
fix timing issues with display driver
This commit is contained in:
parent
245108a07a
commit
7a0f59c9f6
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@ -1,4 +1,4 @@
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from amaranth import Module, Cat, Mux, ShapeLike, Signal, Assert, Array
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from amaranth import Module, Cat, Mux, Print, ShapeLike, Signal, Assert, Array
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from amaranth.build import Platform
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from amaranth.build import Platform
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from amaranth.lib import wiring, data
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from amaranth.lib import wiring, data
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from amaranth.lib.wiring import In, Out
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from amaranth.lib.wiring import In, Out
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@ -80,6 +80,63 @@ class SwapBuffer(wiring.Component):
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return m
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return m
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class DisplayClock(wiring.Component):
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"""Generates the display clock automatically with the correct delay
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when start is asserted. Stops when `done` is strobed.
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Can either be used as a /2 clock divider or a /4 with the `double_fetch` parameter.
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The startup delay is chosen based on the mode or can be set with `startup_delay`
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"""
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def __init__(self, *, double_fetch: bool = True, startup_delay=None, src_loc_at=0):
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self.double_fetch = double_fetch
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if startup_delay is None:
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self.startup_delay = 4 if double_fetch else 1 # FIXME: choose right values.
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else:
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self.startup_delay = startup_delay
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super().__init__(
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{
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"start": In(1),
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"done": In(1),
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"clk": Out(1),
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},
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src_loc_at=src_loc_at,
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)
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def elaborate(self, platform: Platform) -> Module:
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m = Module()
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counter = Signal(range(max(self.startup_delay, 2) + 1))
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with m.FSM():
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with m.State("init"):
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m.d.sync += [counter.eq(0), self.clk.eq(0)]
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with m.If(self.start == 1):
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m.next = "warmup"
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with m.State("warmup"):
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m.d.sync += counter.eq(counter + 1)
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with m.If(counter == self.startup_delay - 1):
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m.next = "run"
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m.d.sync += counter.eq(0)
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with m.State("run"):
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with m.If(self.done == 1):
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m.next = "init"
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if self.double_fetch:
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m.d.sync += [
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self.clk.eq(~counter[1]),
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counter.eq(counter + 1),
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]
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else:
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m.d.sync += [
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self.clk.eq(~counter),
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counter.eq(~counter),
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]
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return m
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class Hub75DataDriver(wiring.Component):
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class Hub75DataDriver(wiring.Component):
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def __init__(
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def __init__(
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self,
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self,
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@ -117,6 +174,7 @@ class Hub75DataDriver(wiring.Component):
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m = Module()
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m = Module()
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counter = Signal(32)
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counter = Signal(32)
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m.d.sync += counter.eq(counter + 1)
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pixnum = Signal(range(self.panel_length), init=self.panel_length - 1)
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pixnum = Signal(range(self.panel_length), init=self.panel_length - 1)
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if self.double_fetch:
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if self.double_fetch:
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@ -137,7 +195,7 @@ class Hub75DataDriver(wiring.Component):
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m.d.sync += [
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m.d.sync += [
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self.done.eq(0),
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self.done.eq(0),
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counter.eq(0),
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counter.eq(0),
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pixnum.eq(pixnum.reset),
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pixnum.eq(pixnum.init),
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]
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]
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if self.double_fetch:
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if self.double_fetch:
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m.d.sync += pixrow.eq(0)
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m.d.sync += pixrow.eq(0)
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@ -145,30 +203,31 @@ class Hub75DataDriver(wiring.Component):
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m.d.sync += self.bram.en.eq(1)
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m.d.sync += self.bram.en.eq(1)
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m.next = "prefetch" if self.double_fetch else "writerow"
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m.next = "prefetch" if self.double_fetch else "writerow"
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with m.State("prefetch"):
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with m.State("prefetch"):
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# TODO: do we need this
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# Allow the BRAM to settle after being enabled.
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m.d.sync += counter.eq(0)
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m.next = "writerow"
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m.next = "writerow"
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with m.State("writerow"):
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with m.State("writerow"):
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if self.double_fetch:
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if self.double_fetch:
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c = counter[0:1]
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c = counter[0:2]
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with m.If(c == 0):
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with m.If(c == 0b0):
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m.d.sync += [
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m.d.sync += [
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self.data.rgb0.eq(ram_rgb_slice),
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self.data.rgb0.eq(ram_rgb_slice),
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pixrow.eq(1),
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pixrow.eq(1),
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]
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]
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with m.If(c == 1):
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with m.If(c == 0b01):
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m.d.sync += self.data.rgb1.eq(ram_rgb_slice)
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with m.If(c == 2):
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pass
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pass
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with m.If(c == 0b10):
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with m.If(c == 3):
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m.d.sync += self.data.rgb1.eq(ram_rgb_slice)
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m.d.sync += [
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m.d.sync += [
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counter.eq(0),
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pixnum.eq(pixnum - 1),
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pixnum.eq(pixnum - 1),
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pixrow.eq(0),
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pixrow.eq(0),
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]
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]
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with m.If(pixnum == 0):
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with m.If(pixnum == 0):
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m.next = "done"
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m.next = "done"
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with m.If(c == 0b11):
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m.d.sync += counter.eq(0)
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else:
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else:
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with m.If(counter[0] == 0):
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with m.If(counter[0] == 0):
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m.d.sync += [
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m.d.sync += [
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@ -189,74 +248,6 @@ class Hub75DataDriver(wiring.Component):
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return m
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return m
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class Hub75StringDriver(wiring.Component):
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"""A data driver for Hub75 panels. This accesses the line memory and feeds out the data.
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It is controlled by a Hub75Coordinator to signal when it should run and what bit of the data
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it should send.
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"""
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def __init__(self, panel_length: int = 128, *, src_loc_at=0):
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self.panel_length = panel_length
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super().__init__(
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{
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"bcm_select": In(3),
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"done": Out(1),
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"start": In(1),
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"bram": In(
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ReadPort.Signature(
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addr_width=ceil_log2(panel_length),
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shape=data.ArrayLayout(Rgb666Layout, 2),
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)
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),
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"display_out": Out(Hub75Data()),
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},
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src_loc_at=src_loc_at,
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)
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def elaborate(self, platform: Platform) -> Module:
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m = Module()
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self._counter = counter = Signal(32) # unused count is optimized out
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m.d.sync += counter.eq(counter + 1)
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ram_rgb0_slice = self.bram.data[0].channel_slice(self.bcm_select)
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ram_rgb1_slice = self.bram.data[1].channel_slice(self.bcm_select)
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m.d.comb += [
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self.display_out.rgb0.eq(ram_rgb0_slice),
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self.display_out.rgb1.eq(ram_rgb1_slice),
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]
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m.d.sync += Assert(self.bcm_select < 6)
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pixnum = Signal(range(self.panel_length), init=self.panel_length - 1)
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m.d.comb += self.bram.addr.eq(pixnum)
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with m.FSM():
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with m.State("init"):
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m.d.sync += [
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self.done.eq(0),
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counter.eq(0),
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pixnum.eq(self.panel_length - 1),
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]
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with m.If(self.start == 1):
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m.d.sync += self.bram.en.eq(1)
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m.next = "writerow"
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with m.State("writerow"):
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with m.If(counter[0] == 0):
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# do nothing
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pass
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with m.If((counter[0] == 1) & (pixnum != 0)):
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m.d.sync += pixnum.eq(pixnum - 1)
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with m.Else():
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m.next = "done"
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with m.State("done"):
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m.d.sync += [self.done.eq(1), self.bram.en.eq(0)]
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m.next = "init"
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return m
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class Hub75Coordinator(wiring.Component):
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class Hub75Coordinator(wiring.Component):
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"""A shared-control hub75 driver"""
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"""A shared-control hub75 driver"""
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@ -285,7 +276,9 @@ class Hub75Coordinator(wiring.Component):
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for i in range(self.n_strings):
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for i in range(self.n_strings):
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sb = SwapBuffer(depth=128, shape=data.ArrayLayout(Rgb666Layout, 2))
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sb = SwapBuffer(depth=128, shape=data.ArrayLayout(Rgb666Layout, 2))
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bufs.append(sb)
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bufs.append(sb)
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stringdriver = Hub75StringDriver(128)
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stringdriver = Hub75DataDriver(
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128, data_shape=Rgb666Layout, double_fetch=False
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)
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strings.append(stringdriver)
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strings.append(stringdriver)
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wiring.connect(m, sb.read_port, stringdriver.bram_port)
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wiring.connect(m, sb.read_port, stringdriver.bram_port)
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m.d.comb += [
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m.d.comb += [
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@ -0,0 +1,7 @@
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import pytest
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@pytest.fixture()
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def simfixture(request: pytest.FixtureRequest, tmp_path):
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pass
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@ -7,9 +7,9 @@ import pytest
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from groovylight.common import Rgb888Layout, Rgb666Layout
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from groovylight.common import Rgb888Layout, Rgb666Layout
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from groovylight.hub75 import (
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from groovylight.hub75 import (
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DisplayClock,
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Hub75Coordinator,
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Hub75Coordinator,
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Hub75DataDriver,
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Hub75DataDriver,
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Hub75StringDriver,
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SwapBuffer,
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SwapBuffer,
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)
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)
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@ -42,65 +42,62 @@ def test_swapbuffer():
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sim.run_until(1e-6 * 1000)
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sim.run_until(1e-6 * 1000)
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def test_stringdriver():
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# the string driver test must
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# 1. finish
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# 2. strobe through all of the data in the array
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# 3. slice the correct bit from the data.
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m = Module()
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m.submodules.dut = dut = Hub75StringDriver()
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m.submodules.mem = mem = Memory(
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shape=data.ArrayLayout(Rgb666Layout, 2), depth=128, init=[]
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)
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port = mem.read_port()
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wiring.connect(m, port, dut.bram)
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async def testbench(ctx):
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# select a bit, strobe start, read values, test against known.
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ctx.set(dut.bcm_select, 5)
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ctx.set(dut.start, 1)
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await ctx.tick()
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ctx.set(dut.start, 0)
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assert ctx.get(dut.bram.en) == 1
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pass
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sim = Simulator(m)
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sim.add_clock(1e-6)
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with sim.write_vcd("output.vcd"):
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sim.run_until(1e-6 * 1000)
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def test_datadriver():
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def test_datadriver():
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# the string driver test must
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# the string driver test must
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# 1. finish
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# 1. finish
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# 2. strobe through all of the data in the array
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# 2. strobe through all of the data in the array
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# 3. slice the correct bit from the data.
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# 3. slice the correct bit from the data.
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memdata = [{"red": x, "green": x, "blue": x} for x in range(256)]
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m = Module()
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m = Module()
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m.submodules.dut = dut = Hub75DataDriver()
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m.submodules.dut = dut = Hub75DataDriver()
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m.submodules.mem = mem = Memory(shape=Rgb888Layout, depth=256, init=[])
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m.submodules.mem = mem = Memory(shape=Rgb888Layout, depth=256, init=memdata)
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m.submodules.clocker = clocker = DisplayClock()
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m.d.comb += [
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clocker.start.eq(dut.start),
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clocker.done.eq(dut.done),
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]
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port = mem.read_port()
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port = mem.read_port()
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wiring.connect(m, port, dut.bram)
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wiring.connect(m, port, dut.bram)
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async def testbench(ctx):
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async def testbench(ctx):
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# select a bit, strobe start, read values, test against known.
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# select a bit, strobe start, read values, test against known.
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ctx.set(dut.bcm_select, 5)
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ctx.set(dut.bcm_select, 7)
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ctx.set(dut.start, 1)
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ctx.set(dut.start, 1)
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await ctx.tick()
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await ctx.tick()
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ctx.set(dut.start, 0)
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ctx.set(dut.start, 0)
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assert ctx.get(dut.bram.en) == 1
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assert ctx.get(dut.bram.en) == 1
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await ctx.tick().until(dut.done == 1)
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async def rgbtest(ctx):
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await ctx.tick().until(dut.start == 1)
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counter = 127
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bitslice = 7
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async for _, rgb0, rgb1 in ctx.posedge(clocker.clk).sample(dut.data.rgb0, dut.data.rgb1):
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assert counter >= 0, "should not do more than 128 clocks"
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e0 = ctx.get(mem.data[counter << 1])
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e1 = ctx.get(mem.data[(counter << 1) + 1])
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print(counter)
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for r, e in [(rgb0, e0), (rgb1, e1)]:
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assert r.red == (e.red >> bitslice) & 1
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assert r.green == (e.green >> bitslice) & 1
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assert r.blue == (e.blue >> bitslice) & 1
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counter = counter - 1
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sim = Simulator(m)
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sim = Simulator(m)
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sim.add_clock(1e-6)
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sim.add_clock(1e-6)
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sim.add_testbench(testbench)
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sim.add_testbench(rgbtest, background=True)
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with sim.write_vcd("output.vcd"):
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with sim.write_vcd("output.vcd"):
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sim.run_until(1e-6 * 1000)
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sim.run()
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# sim.run_until(1e-6 * 4000)
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@pytest.mark.skip()
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@pytest.mark.skip()
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def test_hub75():
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def test_hub75_coordinator():
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m = Module()
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m = Module()
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m.submodules.dut = dut = Hub75Coordinator(1)
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m.submodules.dut = dut = Hub75Coordinator(1)
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