sdram simulation

src/groovylight/platforms/cxxrtl_sim.py

@@ -17,6 +17,7 @@ from groovylight import hub75
 def emit_cxxrtl(config):
     m = Module()
     m.submodules.coordinator = crd = hub75.Hub75Coordinator(config.geom)
-    cxxrtl.convert(m, ports=[])
+    out = cxxrtl.convert(m, ports=[])
-
+    with open("model.hpp", 'w') as f:
+        f.write(out)
 

src/groovylight/sdram.py

@@ -4,6 +4,7 @@
 from amaranth import Module, Cat, Signal, Assert, unsigned
 from amaranth.build import Platform
 from amaranth.lib import wiring, data, enum
+from amaranth.lib.memory import ceil_log2
 from amaranth.lib.wiring import In, Out
 
 
@@ -14,27 +15,6 @@ from amaranth.lib.wiring import In, Out
 # 8 megabytes data.
 
 
-class SDRAMSignature(wiring.Signature):
-    """Signature of a variable-size sdram. Data is split between in/out and has out_en"""
-
-    def __init__(self, addr_width, data_width=32, bank_width=2):
-        super().__init__(
-            {
-                "nCS": Out(1),
-                "cke": Out(1),
-                "nRAS": Out(1),
-                "nCAS": Out(1),
-                "nWE": Out(1),
-                "addr": Out(addr_width),
-                "data_out": Out(data_width),
-                "data_in": In(data_width),
-                # todo: use dqm
-                "data_wren": Out(1),
-                "bank_cs": Out(bank_width),
-            }
-        )
-
-
 class _WriteBurstLength(enum.Enum, shape=1):
     """MRS Write burst mode"""
 
@@ -73,20 +53,105 @@ class _BurstLength(enum.IntEnum, shape=3):
     FULL_PAGE = 7  # this is 256 words?
 
 
-class _Command(enum.Enum):
+class Command(data.StructLayout):
-    """Command set for SDRAM"""
+    class Kind(enum.Enum):
+        """Command set for SDRAM"""
 
-    MRS_WRITE = 0
+        NOP = 0
-    ACTIVATE = 1
+        ACTIVATE = 1
-    PRECHARGE = 2
+        PRECHARGE = 2
-    WRITE = 3
+        WRITE = 3
-    READ = 4
+        READ = 4
-    CBR = 5  # auto refresh
+        CBR = 5  # auto refresh, CKE = high
-    SELF_REFRESH = 6
+        SELF_REFRESH = 6  # cke = low
-    BRST_STOP = 7
+        BRST_STOP = 7
-    NOP = 8
+        MRS_WRITE = 8
+
+    def __init__(self):
+        super().__init__(
+            {
+                "valid": 1,
+                "kind": self.Kind,
+                "param": data.UnionLayout(
+                    {
+                        "activate": data.StructLayout(
+                            {"row": unsigned(10), "bank": unsigned(2)}
+                        ),
+                        "precharge": data.StructLayout({"bank": unsigned(2), "all": 1}),
+                        "write": data.StructLayout(
+                            {
+                                "column": unsigned(3),
+                            }
+                        ),
+                        "read": data.StructLayout(
+                            {
+                                "column": unsigned(3),
+                            }
+                        ),
+                        "cbr": 0,
+
+                    }
+                ),
+            }
+        )
+
+    # valid: 1
+    # kind : Kind
+    # param: data.UnionLayout({
+    #     })
 
 
-class BankController(wiring.Component):
+class MRSRegister(data.FlexibleLayout):
-    """Manages a single Bank. Has a bank locking/state tracker,
+    """Represents the ESMT MRS Register"""
-    can issue commands"""
+
+
+class SDRAMSignature(wiring.Signature):
+    """Signature of a variable-size sdram. Data is split between in/out and has out_en"""
+
+    def __init__(self, addr_width, data_width=32, n_banks=4):
+        if data_width not in [8, 16, 32, 64, 128]:
+            raise RuntimeError("data width must be one of [8,16,32,64,128]")
+        super().__init__(
+            {
+                "nCS": Out(1),
+                "cke": Out(1),
+                "nRAS": Out(1),
+                "nCAS": Out(1),
+                "nWE": Out(1),
+                "addr": Out(addr_width),
+                "data_out": Out(data_width),
+                "data_in": In(data_width),
+                "dqm": Out(ceil_log2(data_width)),
+                "data_wren": Out(1),
+                "bank_cs": Out(ceil_log2(n_banks)),
+            }
+        )
+
+    # TODO: define a view for this class that gives greater control.
+    def create(self, *, path=None, src_loc_at=0):
+        return SDRAMInterface(self, path=path, src_loc_at=1 + src_loc_at)
+
+
+class SDRAMInterface(wiring.PureInterface):
+    """Interface to define operations/meanings to the SDRAM Signature."""
+
+    # def process_command(self, cmd: _Command):
+    #     pass
+
+
+_example_timings = {
+    "tRRD": 12,  # Row active to row active delay
+    "tRCD": 18,  # Row active to column active delay
+    "tRP": 18,  # Row prrecharge time,
+    "tRAS": (42, 100),  # row active time
+    "tRC": 60,  # row cycle time
+}
+
+
+class SDRamController(wiring.Component):
+    """Manages SDRAM by automatically refreshing it and reading operations off of a wishbone bus"""
+
+    def __init__(self, timings, *, src_loc_at=0):
+        self._timings = timings
+
+        super().__init__({}, src_loc_at=src_loc_at)

src/groovylight/top.py

@@ -4,6 +4,6 @@
 from amaranth import Signal
 from amaranth.lib import wiring, data
 
-from .hub75
+from .hub75 import Hub75Coordinator
-
+from .sdram import SDRamController