migrate tests

src/groovylight/tests/test_hub75.py

@@ -0,0 +1,38 @@
+from amaranth import Array, Module, Cat, Signal, Assert, unsigned
+from amaranth.build import Platform
+from amaranth.lib import wiring, data
+from amaranth.lib.wiring import In, Out
+from amaranth.lib.memory import Memory, WritePort
+from amaranth.sim import Simulator
+
+from ..bitslicer import Hub75StringDriver, Rgb666Layout
+
+
+def test_stringdriver():
+    # the string driver test must
+    # 1. finish
+    # 2. strobe through all of the data in the array
+    # 3. slice the correct bit from the data.
+    m = Module()
+    m.submodules.dut = dut = Hub75StringDriver()
+    m.submodules.mem = mem = Memory(
+        shape=data.ArrayLayout(Rgb666Layout, 2), depth=128, init=[]
+    )
+    port = mem.read_port()
+
+    wiring.connect(m, port, dut.bram_port)
+
+    async def testbench(ctx):
+        # select a bit, strobe start, read values, test against known.
+        ctx.set(dut.bcm_select, 5)
+        ctx.set(dut.start, 1)
+        await ctx.tick()
+        ctx.set(dut.start, 0)
+        assert ctx.get(dut.bram_port.en) == 1
+        pass
+
+    sim = Simulator(m)
+    sim.add_clock(1e-6)
+
+    with sim.write_vcd("output.vcd"):
+        sim.run_until(1e-6 * 1000)

src/groovylight/tests/test_swapbuffer.py

@@ -0,0 +1,34 @@
+from amaranth import Array, Module, Cat, Signal, Assert, unsigned
+from amaranth.build import Platform
+from amaranth.lib import wiring, data
+from amaranth.lib.wiring import In, Out
+from amaranth.lib.memory import Memory, WritePort
+from amaranth.sim import Simulator
+
+from ..bitslicer import Hub75StringDriver, Rgb666Layout, SwapBuffer
+
+
+def test_swapbuffer():
+    dut = SwapBuffer(Rgb666Layout, 512)
+    sim = Simulator(dut)
+    sim.add_clock(1e-6)
+
+    async def testbench(ctx):
+        init_color = {"red": 0, "green": 0, "blue": 0}
+        test_color = {"red": 8, "green": 8, "blue": 8}
+        ctx.set(dut.selector, 0)
+        ctx.set(dut.write_port.addr, 1)
+        ctx.set(dut.read_port.addr, 1)
+        ctx.set(dut.write_port.data, test_color)
+        await ctx.tick()
+        # assert that the read port addr 1 = 0
+        assert ctx.get(dut.read_port.data) == init_color
+        # swap buffer
+        ctx.set(dut.selector, 1)
+        await ctx.tick().repeat(2) # takes two clocks after switching selector to output data.
+        assert ctx.get(dut.read_port.data) == test_color
+    
+    # TODO: add more assertions/verification
+    sim.add_testbench(testbench)
+    with sim.write_vcd("output.vcd"):
+        sim.run_until(1e-6 * 1000)