From 2a8c70bab2b9aefcd2d3688c57035e52f455c9e9 Mon Sep 17 00:00:00 2001
From: saji <saji@saji.dev>
Date: Thu, 2 May 2024 20:30:51 -0500
Subject: [PATCH] fix bit-loading latency using comb logic

make frame counter for generating data
---
 verilog/coordinator.sv |  9 +++++++--
 verilog/hub75e.sv      | 12 ++++++++----
 verilog/pixgen.sv      |  3 ++-
 3 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/verilog/coordinator.sv b/verilog/coordinator.sv
index f2afc1d..b29af0e 100644
--- a/verilog/coordinator.sv
+++ b/verilog/coordinator.sv
@@ -8,6 +8,8 @@ module coordinator (
     output reg [4:0] display_addr
 );
 
+  reg [11:0] frame_counter;
+
   // pixgen signals
   reg pixgen_start;
   reg [8:0] x;
@@ -22,7 +24,8 @@ module coordinator (
       .x(x),
       .y(y),
       .rgb(pix_rgb0),
-      .done(pix_done[0])
+      .done(pix_done[0]),
+      .frame(frame_counter[11:4])
   );
   pixgen pix1 (
       .clk(clk),
@@ -30,7 +33,8 @@ module coordinator (
       .x(x),
       .y(y + 9'd32),
       .rgb(pix_rgb1),
-      .done(pix_done[1])
+      .done(pix_done[1]),
+      .frame(frame_counter[11:4])
   );
 
 
@@ -138,6 +142,7 @@ module coordinator (
         if (display_addr == 31) begin
           state <= StateInit;
         end else begin
+          frame_counter <= frame_counter + 1;
           state <= StateStartFrame;
         end
       end
diff --git a/verilog/hub75e.sv b/verilog/hub75e.sv
index 33c3244..fbdc88f 100644
--- a/verilog/hub75e.sv
+++ b/verilog/hub75e.sv
@@ -47,11 +47,15 @@ module hub75e (
   // short!
 
   wire should_clock, should_expose;
-  assign should_clock  = (counter < ROW_DEPTH * 2 + 1); // the plus 1 is for the falling edge!
+  assign should_clock  = (counter < ROW_DEPTH * 2 + 1);  // the plus 1 is for the falling edge!
   assign should_expose = (counter < (16 << bcm_shift + 1)) && (bcm_shift != 7);
 
   reg [7:0] pixnum;
   assign pixbuf_addr = {bcm_shift, pixnum};
+  always @(*) begin
+    panel_rgb0 = pixbuf_data[2:0];
+    panel_rgb1 = pixbuf_data[5:3];
+  end
 
   always_ff @(posedge clk) begin
     counter <= counter + 1;
@@ -73,8 +77,8 @@ module hub75e (
           display_clk <= counter[0];
           if (~counter[0]) begin
             // the data from the previous cycle is now ready.
-            panel_rgb0 <= pixbuf_data[2:0];
-            panel_rgb1 <= pixbuf_data[5:3];
+            // panel_rgb0 <= pixbuf_data[2:0];
+            // panel_rgb1 <= pixbuf_data[5:3];
             // write it out!
           end else begin
             // update the bram address so it's ready at the next clock cycle.
@@ -91,7 +95,7 @@ module hub75e (
         if (~should_clock && ~should_expose) begin
           counter <= 0;
           pixnum <= 0;
-          state   <= StateLatchout;
+          state <= StateLatchout;
           display_clk <= 0;
         end
       end
diff --git a/verilog/pixgen.sv b/verilog/pixgen.sv
index 8509dc1..5e36a56 100644
--- a/verilog/pixgen.sv
+++ b/verilog/pixgen.sv
@@ -7,6 +7,7 @@ module pixgen #(
     input start,
     input [X_DEPTH-1:0] x,
     input [Y_DEPTH-1:0] y,
+    input [7:0] frame,
     output reg [RGB_DEPTH-1:0] rgb,
     output reg done
 );
@@ -16,7 +17,7 @@ module pixgen #(
 always @(posedge clk) begin
   if (start) begin
     done <= 1;
-    rgb <= { 8'b0, x[7:0], y[7:0] };
+    rgb <= { x[6:0], 1'b0, frame, y[5:0], 2'b0};
   end
   else done <= 0;
 end