generated from saji/ecp5-template
wip: line scan test
also factored out some code.
This commit is contained in:
parent
da9c0c05a7
commit
2a7908eae9
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@ -41,6 +41,8 @@ target_sources(sim PRIVATE
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src/main.cpp
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)
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target_include_directories(sim PRIVATE inc/)
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list(APPEND VSOURCES ../verilog/hub75e.sv ../verilog/lineram.v)
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150
sim/inc/devices.hpp
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150
sim/inc/devices.hpp
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@ -0,0 +1,150 @@
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// Project-specific cosimuluated devices.
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#pragma once
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#include "tests.hpp"
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#include "Vhub75e.h"
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// slices the RGB values for us.
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uint8_t rgb_slice(uint32_t rgb, uint8_t bit) {
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if (bit > 8) {
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// todo: panic
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return 0;
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}
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uint8_t r = (rgb >> (16 + bit)) & 1;
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uint8_t g = (rgb >> (8 + bit)) & 1;
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uint8_t b = (rgb >> bit) & 1;
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return (r << 2) & (g << 1) & (b << 1);
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}
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void rgb_unslice(unsigned int &rgb, uint8_t bits, uint8_t bitpos) {
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if (bitpos > 7 || bits > 0b111) {
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// TODO: panic.
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return;
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}
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auto r = (bits >> 2) & 1;
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auto g = (bits >> 1) & 1;
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auto b = (bits >> 0) & 1;
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rgb |= r << bitpos << 16;
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rgb |= g << bitpos << 8;
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rgb |= b << bitpos << 0;
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}
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class HUB75Reciever : public CosimulatedDevice {
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typedef std::vector<unsigned char> row_array;
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int xsize;
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int ysize;
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row_array row0{};
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row_array row1{};
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// the previous row values that were latched in.
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std::vector<std::pair<row_array, row_array>> past_rows{};
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// the pulse width for each output, in clock cycles.
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std::vector<int> pulse_widths{};
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int bit_position = 7; // the bit that is currently being shifted in
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int output_period_cnt;
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// if oe = 0, count clocks. when oe = 1, store value into
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// pulse_widths[display_bit];
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// previous latch value, used to identify when to latch.
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unsigned char prev_latch = 0;
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// previous display clock value, used to detect rising edge.
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unsigned char prev_display_clk = 0;
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unsigned char prev_clk = 0;
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unsigned char prev_oe = 1; // assuming starting high.
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// references to the panel driver signals.
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VL_IN8(&display_clk, 0, 0);
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VL_IN8(&out_enable, 0, 0);
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VL_IN8(&latch, 0, 0);
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VL_IN8(&rgb0, 2, 0);
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VL_IN8(&rgb1, 2, 0);
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VL_IN8(&clk, 0, 0);
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public:
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HUB75Reciever(int xsize, int ysize, const Vhub75e &dut)
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: clk(dut.clk), display_clk(dut.display_clk), out_enable(dut.out_enable),
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latch(dut.latch), rgb0(dut.panel_rgb0), rgb1(dut.panel_rgb1) {
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this->xsize = xsize;
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this->ysize = ysize;
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row0.clear();
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prev_oe = out_enable;
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prev_display_clk = display_clk;
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prev_latch = latch;
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prev_clk = clk;
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};
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// evaluates the reciever.
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virtual void tick() override {
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if (prev_display_clk == 0 && display_clk == 1) {
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// display clock rising edge.
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row0.push_back(rgb0);
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row1.push_back(rgb1);
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}
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if (prev_latch == 0 && latch == 1) {
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// latch in the data: reverse the rows, and pu
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std::reverse(row0.begin(), row0.end());
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std::reverse(row1.begin(), row1.end());
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past_rows.push_back(std::pair(row0, row1));
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row0.clear();
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row1.clear();
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}
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if (prev_clk == 0 && clk == 1) {
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if (out_enable == 0) {
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if (prev_oe == 1) {
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// falling edge.
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output_period_cnt = 1;
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} else {
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output_period_cnt++;
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}
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} else { // out_enable == 1
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if (prev_oe == 1) {
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// do nothing
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}
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if (prev_oe == 0) {
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// rising edge
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pulse_widths.push_back(output_period_cnt);
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}
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}
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}
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// update previous values
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prev_display_clk = display_clk;
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prev_latch = latch;
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prev_oe = out_enable;
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prev_clk = clk;
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}
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const auto &get_past_rows() { return this->past_rows; }
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const std::vector<int> &get_pulse_widths() { return this->pulse_widths; }
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// return the RGB version.
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std::pair<std::vector<unsigned int>, std::vector<unsigned int>> transpose() {
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auto r0rgb = std::vector<unsigned int>(xsize, 0);
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auto r1rgb = std::vector<unsigned int>(xsize, 0);
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auto bitdepth = pulse_widths.size();
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// TODO: use more sophisticated slicing.
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auto slice = bitdepth - 1;
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for (const auto &[row0slice, row1slice] : this->past_rows) {
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for (int i = 0; i < row0slice.size(); i++) {
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rgb_unslice(r0rgb[i], row0slice[i], slice);
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rgb_unslice(r1rgb[i], row1slice[i], slice);
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}
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slice--;
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}
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return std::pair(r0rgb, r1rgb);
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}
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};
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204
sim/inc/tests.hpp
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204
sim/inc/tests.hpp
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@ -0,0 +1,204 @@
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// Common Verilator Simulation/test constructs.
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// Includes a simulation-fixture useful for writing tests.
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#pragma once
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include <cstdint>
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#include <span>
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#include <memory>
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#include <queue>
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#include <vector>
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// represents a generic co-simulated device.
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// While this abstract class is very simple, it enables dynamic behavior to be added to the
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// simulation fixture.
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class CosimulatedDevice {
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public:
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virtual ~CosimulatedDevice(){};
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virtual void tick() = 0;
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};
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// Simple stimulus class used to trigger basic operations
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class PulseStimulus : public CosimulatedDevice {
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unsigned long width;
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unsigned char &signal;
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unsigned long counter = 0;
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public:
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PulseStimulus(unsigned char &signal, unsigned long width) : signal(signal) {
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this->width = width;
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}
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virtual void tick() override {
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if (counter < width) {
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signal = 1;
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} else {
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signal = 0;
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}
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counter++;
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}
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};
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class FakeBRAM : public CosimulatedDevice {
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std::array<unsigned long, 512> ram{};
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std::queue<unsigned long> addr_lookup_q;
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unsigned short &addr_in;
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unsigned long &data_out;
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unsigned char &clk;
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public:
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FakeBRAM(int latency, unsigned char &clk, unsigned short &addr_in,
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unsigned long &data_out)
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: addr_lookup_q(), addr_in(addr_in), data_out(data_out), clk(clk) {
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for (int i = 0; i < latency; i++) {
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addr_lookup_q.push(0);
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}
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for (int i = 0; i < ram.size(); i++) {
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ram[i] = i + 3;
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}
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};
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FakeBRAM(int latency, unsigned char &clk, unsigned short &addr_in,
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unsigned long &data_out, std::array<unsigned long, 512> ram)
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: addr_lookup_q(), addr_in(addr_in), data_out(data_out), clk(clk),
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ram(ram) {
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for (int i = 0; i < latency; i++) {
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addr_lookup_q.push(0);
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}
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}
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void tick() {
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// we push and pop in the same tick: this way we keep the queue the same
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// size, acting as a pipeline delay.
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addr_lookup_q.push(addr_in);
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auto addr_to_load = addr_lookup_q.front();
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addr_lookup_q.pop();
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data_out = ram.at(addr_to_load);
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}
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// TODO: allow accessing/setting the data
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const std::span<uint64_t, 512> get() { return this->ram; }
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void write(unsigned short addr, unsigned long data) { ram[addr] = data; }
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};
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// test fixture to reduce amount of runtime code.
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// Supports:
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// adding external modules
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// running the test
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// storing if the done flag was raised (or not)
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//
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// TODO: tracing.
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template <typename DUT> class VerilatorTestFixture {
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public:
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enum class FinishReason { Ok, Timeout };
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private:
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// we call .tick() on all of these. They are bound externally to the DUT.
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std::vector<std::shared_ptr<CosimulatedDevice>> external_devices;
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std::unique_ptr<VerilatedContext> ctx;
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std::unique_ptr<DUT> dut;
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unsigned long timeout =
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1000000; // clock cycles to execute before ending the simulation.
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unsigned long simtime = 0;
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unsigned long posedge = 0;
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// stores the termination-condition for the simulation.
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// if false, it means we timed out. If true, our done_condition returned true.
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enum FinishReason reason;
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typedef std::function<bool(DUT &, unsigned long)> done_callback;
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// callback function to determine execution completion.
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// This can be used to add arbitrary finish-conditions to the execution.
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// If the function returns true, we set the done_set boolean to true;
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done_callback done_check;
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std::unique_ptr<VerilatedVcdC> trace;
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public:
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// Create a new test fixture with a given timeout. Everything else (including
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// done-condition) can be set later.
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VerilatorTestFixture() {
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ctx = std::make_unique<VerilatedContext>();
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dut = std::make_unique<DUT>(ctx.get(), "dut");
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dut->eval(); // let values settle before adding modules.
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}
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void set_timeout(unsigned long new_timeout) { this->timeout = new_timeout; }
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void set_done_callback(done_callback d) { this->done_check = d; }
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void add_module(std::shared_ptr<CosimulatedDevice> device) {
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external_devices.push_back(device);
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}
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void enable_trace(std::string name) {
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if (!trace) {
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ctx->traceEverOn(true);
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trace = std::make_unique<VerilatedVcdC>();
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dut->trace(trace.get(), 99);
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trace->open(name.c_str());
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}
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}
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void exec() {
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bool done = false;
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dut->eval(); // pre-eval.
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while (!done) {
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dut->clk ^= 1;
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dut->eval();
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if (trace) {
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trace->dump(10 * simtime);
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}
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if (dut->clk == 1) {
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posedge++;
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}
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if (done_check) {
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if (done_check(*dut, posedge)) {
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reason = FinishReason::Ok;
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done = true;
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}
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}
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if (posedge >= timeout) {
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reason = FinishReason::Timeout;
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done = true;
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}
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// run our external devices
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for (auto dev : external_devices) {
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dev->tick();
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}
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if (trace) {
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trace->dump(10 * simtime + 5);
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}
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dut->eval(); // allow combinational logic to settle if it's being set on
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// the negative clock.
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if (trace) {
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trace->dump(10 * simtime + 6);
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}
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simtime++;
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}
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if (trace) {
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// close the trace.
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trace->close();
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}
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}
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// return a reference to the DUT itself. Useful for bespoke tests.
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const DUT &get() { return *dut; }
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const FinishReason get_reason() { return reason; }
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};
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285
sim/src/main.cpp
285
sim/src/main.cpp
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@ -1,163 +1,14 @@
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#include "Vhub75e.h"
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#include "tests.hpp"
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#include "devices.hpp"
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#include "verilated.h"
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#include "verilated_vcd_c.h"
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#include <array>
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#include <catch2/catch_test_macros.hpp>
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#include <catch2/matchers/catch_matchers.hpp>
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#include <catch2/matchers/catch_matchers_all.hpp>
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#include <cstdint>
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#include <memory>
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#include <queue>
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#include <stdio.h>
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#include <vector>
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class CosimulatedDevice {
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public:
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virtual ~CosimulatedDevice(){};
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virtual void tick() = 0;
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};
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// slices the RGB values for us.
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uint8_t rgb_slice(uint32_t rgb, uint8_t bit) {
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if (bit > 8) {
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// todo: panic
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return 0;
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}
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uint8_t r = (rgb >> (16 + bit)) & 1;
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uint8_t g = (rgb >> (8 + bit)) & 1;
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uint8_t b = (rgb >> bit) & 1;
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return (r << 2) & (g << 1) & (b << 1);
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}
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class HUB75Reciever : public CosimulatedDevice {
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typedef std::vector<unsigned char> row_array;
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int xsize;
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int ysize;
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row_array row_upper{};
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row_array row_lower{};
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// the previous row values that were latched in.
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std::vector<row_array> past_rows{};
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// the pulse width for each output, in clock cycles.
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std::vector<int> pulse_widths{};
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int bit_position = 7; // the bit that is currently being shifted in
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int output_period_cnt;
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// if oe = 0, count clocks. when oe = 1, store value into
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// pulse_widths[display_bit];
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// previous latch value, used to identify when to latch.
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unsigned char prev_latch = 0;
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// previous display clock value, used to detect rising edge.
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unsigned char prev_display_clk = 0;
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unsigned char prev_oe = 0;
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// references to the panel driver signals.
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VL_IN8(&display_clk, 0, 0);
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VL_IN8(&out_enable, 0, 0);
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VL_IN8(&latch, 0, 0);
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VL_IN8(&rgb0, 2, 0);
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VL_IN8(&rgb1, 2, 0);
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public:
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HUB75Reciever(int xsize, int ysize, Vhub75e &dut)
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: display_clk(dut.display_clk), out_enable(dut.out_enable),
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latch(dut.latch), rgb0(dut.panel_rgb0), rgb1(dut.panel_rgb1) {
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this->xsize = xsize;
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this->ysize = ysize;
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row_upper.clear();
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};
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// evaluates the reciever.
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virtual void tick() override {
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if (prev_display_clk == 0 && display_clk == 1) {
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// display clock rising edge.
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row_upper.push_back(rgb0);
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row_lower.push_back(rgb1);
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}
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if (prev_latch == 0 && latch == 1) {
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// latch in the data: reverse the rows, and pu
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std::reverse(row_upper.begin(), row_upper.end());
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past_rows.push_back(row_upper);
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row_upper.clear();
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}
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if (out_enable == 0) {
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if (prev_oe == 1) {
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// falling edge.
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output_period_cnt = 0;
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} else {
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output_period_cnt++;
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}
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} else {
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// rising edge: store the output
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}
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// update previous values
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prev_display_clk = display_clk;
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prev_latch = latch;
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prev_oe = out_enable;
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}
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const std::vector<row_array> &get_past_rows() { return this->past_rows; }
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const std::vector<int> &get_pulse_widths() { return this->pulse_widths; }
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// return the RGB version.
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std::vector<unsigned int> transpose() {
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auto vec = std::vector<unsigned int>();
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for (auto bits : this->row_upper) {
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}
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return vec;
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}
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};
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class FakeBRAM : public CosimulatedDevice {
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std::array<unsigned long, 512> ram{};
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std::queue<unsigned long> addr_lookup_q;
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unsigned short &addr_in;
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unsigned long &data_out;
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unsigned char &clk;
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public:
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FakeBRAM(int latency, unsigned char &clk, unsigned short &addr_in,
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unsigned long &data_out)
|
||||
: addr_lookup_q(), addr_in(addr_in), data_out(data_out), clk(clk) {
|
||||
for (int i = 0; i < latency; i++) {
|
||||
addr_lookup_q.push(0);
|
||||
}
|
||||
|
||||
for (int i = 0; i < ram.size(); i++) {
|
||||
ram[i] = i;
|
||||
}
|
||||
};
|
||||
|
||||
void tick() {
|
||||
// we push and pop in the same tick: this way we keep the queue the same
|
||||
// size, acting as a pipeline delay.
|
||||
addr_lookup_q.push(addr_in);
|
||||
|
||||
auto addr_to_load = addr_lookup_q.front();
|
||||
addr_lookup_q.pop();
|
||||
data_out = ram.at(addr_to_load);
|
||||
}
|
||||
|
||||
// TODO: allow accessing/setting the data
|
||||
std::array<uint64_t, 512> &dump() { return ram; }
|
||||
|
||||
void write(unsigned short addr, unsigned long data) { ram[addr] = data; }
|
||||
};
|
||||
|
||||
void LineDriverTest(VerilatedContext &ctx) {
|
||||
// create the hub75e driver and run some basic tests
|
||||
|
||||
|
|
@ -206,82 +57,6 @@ void LineDriverTest(VerilatedContext &ctx) {
|
|||
// LineDriverTest(*ctx);
|
||||
// };
|
||||
|
||||
// test fixture to reduce amount of runtime code.
|
||||
// Supports:
|
||||
// adding external modules
|
||||
// running the test
|
||||
// storing if the done flag was raised (or not)
|
||||
//
|
||||
// TODO: tracing.
|
||||
template <typename DUT> class VerilatorTestFixture {
|
||||
// we call .tick() on all of these. They are bound externally to the DUT.
|
||||
std::vector<std::shared_ptr<CosimulatedDevice>> external_devices;
|
||||
std::unique_ptr<VerilatedContext> ctx;
|
||||
std::unique_ptr<DUT> dut;
|
||||
|
||||
unsigned long timeout =
|
||||
1000000; // clock cycles to execute before ending the simulation.
|
||||
unsigned long simtime = 0;
|
||||
unsigned long posedge = 0;
|
||||
|
||||
// stores the termination-condition for the simulation.
|
||||
// if false, it means we timed out. If true, our done_condition returned true.
|
||||
bool done_condition = false;
|
||||
|
||||
typedef std::function<bool(DUT &, unsigned long)> done_callback;
|
||||
// callback function to determine execution completion.
|
||||
// This can be used to add arbitrary finish-conditions to the execution.
|
||||
// If the function returns true, we set the done_set boolean to true;
|
||||
done_callback done_check;
|
||||
|
||||
public:
|
||||
// Create a new test fixture with a given timeout. Everything else (including
|
||||
// done-condition) can be set later.
|
||||
VerilatorTestFixture() {
|
||||
ctx = std::make_unique<VerilatedContext>();
|
||||
dut = std::make_unique<DUT>(ctx.get(), "dut");
|
||||
}
|
||||
|
||||
void set_timeout(unsigned long new_timeout) { this->timeout = new_timeout; }
|
||||
|
||||
void set_done_callback(done_callback d) { this->done_check = d; }
|
||||
|
||||
void add_module(std::shared_ptr<CosimulatedDevice> device) {
|
||||
external_devices.push_back(device);
|
||||
}
|
||||
|
||||
void exec() {
|
||||
bool done = false;
|
||||
while (!done) {
|
||||
dut->clk ^= 1;
|
||||
dut->eval();
|
||||
|
||||
if (dut->clk == 1) {
|
||||
posedge++;
|
||||
}
|
||||
if (done_check) {
|
||||
if (done_check(dut, posedge)) {
|
||||
done_condition = true;
|
||||
done = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (posedge >= timeout) {
|
||||
done = true;
|
||||
}
|
||||
// run our external devices
|
||||
for (auto dev : external_devices) {
|
||||
dev->tick();
|
||||
}
|
||||
dut->eval(); // allow combinational logic to settle if it's being set on the negative clock.
|
||||
simtime++;
|
||||
}
|
||||
}
|
||||
|
||||
// return a reference to the DUT itself. Useful for bespoke tests.
|
||||
DUT &get() { return dut; }
|
||||
};
|
||||
|
||||
TEST_CASE("Hub75 Test") {
|
||||
auto ctx = std::make_unique<VerilatedContext>();
|
||||
// setup DUT
|
||||
|
|
@ -328,9 +103,61 @@ TEST_CASE("Hub75 Test") {
|
|||
|
||||
for (int i = 0; i < rows.size(); i++) {
|
||||
auto r = rows[i];
|
||||
using Catch::Matchers::SizeIs;
|
||||
CHECK_THAT(r, SizeIs(128));
|
||||
}
|
||||
}
|
||||
SECTION("Pulse width") {}
|
||||
}
|
||||
|
||||
TEST_CASE("HUB75E Driver Test") {
|
||||
auto fixture = VerilatorTestFixture<Vhub75e>();
|
||||
// very simple done checker.
|
||||
auto done_check = [](Vhub75e &dut, unsigned long time) {
|
||||
return dut.done == 1;
|
||||
};
|
||||
fixture.set_done_callback(done_check);
|
||||
const Vhub75e &dut = fixture.get();
|
||||
auto stim = std::make_shared<PulseStimulus>(dut.write_trig, 4);
|
||||
fixture.set_timeout(250000);
|
||||
|
||||
fixture.add_module(stim);
|
||||
|
||||
SECTION("Smoke Tests") {
|
||||
fixture.enable_trace("testing.vcd");
|
||||
auto bram = std::make_shared<FakeBRAM>(1, dut.clk, dut.pixbuf_addr,
|
||||
dut.pixbuf_data);
|
||||
fixture.add_module(bram);
|
||||
auto display = std::make_shared<HUB75Reciever>(128, 64, dut);
|
||||
fixture.add_module(display);
|
||||
|
||||
fixture.exec();
|
||||
|
||||
CHECK(fixture.get_reason() ==
|
||||
VerilatorTestFixture<Vhub75e>::FinishReason::Ok);
|
||||
|
||||
auto rows = display->get_past_rows();
|
||||
CHECK(rows.size() == 8);
|
||||
for (int i = 0; i < rows.size(); i++) {
|
||||
auto &[r0, r1] = rows[i];
|
||||
CHECK(r0.size() == 128);
|
||||
CHECK(r1.size() == 128);
|
||||
}
|
||||
// pulse width smoke tests.
|
||||
auto pulses = display->get_pulse_widths();
|
||||
REQUIRE(pulses.size() == rows.size());
|
||||
for (int i = 1; i < pulses.size(); i++) {
|
||||
REQUIRE(pulses[i] == pulses[i - 1] / 2);
|
||||
}
|
||||
auto [row0, row1] = display->transpose();
|
||||
REQUIRE(row0.size() == 128);
|
||||
REQUIRE(row1.size() == 128);
|
||||
auto ram_ref = bram->get();
|
||||
|
||||
CAPTURE(row0);
|
||||
CHECK(std::equal(ram_ref.begin(), ram_ref.begin() + 128, row0.begin(),
|
||||
row0.end()));
|
||||
}
|
||||
SECTION("Line Correctness") {
|
||||
// this is the part where we validate that the line in = line out.
|
||||
// we have to generate different values since the
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in a new issue