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Unit Tests / Test (push) Successful in 2m5s

This commit is contained in:
saji 2024-10-14 11:15:03 -05:00
parent 261dedc4dc
commit 2893262f87

View file

@ -22,6 +22,31 @@ logger = logging.getLogger(__name__)
CoordLayout = data.StructLayout({"x": unsigned(32), "y": unsigned(32)})
class AddressConverter(wiring.Component):
"""Translates display (x,y) into full screen (x,y) based on geometry"""
def __init__(self, geom: DisplayString, *, src_loc_at=0):
self.geom = geom
super().__init__(
{
"input_x": In(geom.dimensions.length),
"addr": In(unsigned(geom.dimensions.addr_bits)),
"output": Out(CoordLayout).array(geom.dimensions.mux),
},
src_loc_at=src_loc_at,
)
def elaborate(self, platform: Platform) -> Module:
m = Module()
for mux in range(self.geom.dimensions.mux):
m.d.comb += self.output[mux].eq(
self.geom.translate_coord(self.input_x, self.addr, mux)
)
return m
class AddressGenerator(wiring.Component):
"""Generates (x,y) sequences corresponding to a display row."""
@ -29,7 +54,8 @@ class AddressGenerator(wiring.Component):
self.geom = geom
super().__init__(
{
"coordstream": Out(stream.Signature(CoordLayout)),
"coordstream": Out( stream.Signature(CoordLayout.array(geom.dimensions.mux))
),
"start": In(1),
"done": Out(1),
"addr": In(geom.dimensions.addr_bits),
@ -43,20 +69,19 @@ class AddressGenerator(wiring.Component):
counter = Signal(self.geom.dimensions.length)
# based on the geometry we generate x,y pairs.
m.submodules.translate = translate = AddressConverter(self.geom)
with m.FSM():
with m.State("init"):
m.d.comb += self.done.eq(0)
m.d.sync += counter.eq(0)
m.d.comb += self.coordstream.valid.eq(0)
with m.If(self.start):
m.next = "run"
with m.State("run"):
if self.geom.rotation == DisplayRotation.LEFTRIGHT:
# default case, +x.
pass
elif self.geom.rotation == DisplayRotation.UPDOWN:
# r 90, +y
# stream data out as long as it's valid.
pass
with m.State("done"):
m.d.comb += self.done.eq(1)