From 245108a07ada30853d251ab9e72f3882e9a2992e Mon Sep 17 00:00:00 2001 From: saji Date: Sat, 28 Sep 2024 17:18:09 -0500 Subject: [PATCH] move swapbuffer test to hub75.py --- src/groovylight/tests/test_hub75.py | 28 +++++++++++++++++++++ src/groovylight/tests/test_swapbuffer.py | 31 ------------------------ 2 files changed, 28 insertions(+), 31 deletions(-) delete mode 100644 src/groovylight/tests/test_swapbuffer.py diff --git a/src/groovylight/tests/test_hub75.py b/src/groovylight/tests/test_hub75.py index 837466e..f4406a3 100644 --- a/src/groovylight/tests/test_hub75.py +++ b/src/groovylight/tests/test_hub75.py @@ -10,9 +10,37 @@ from groovylight.hub75 import ( Hub75Coordinator, Hub75DataDriver, Hub75StringDriver, + SwapBuffer, ) +def test_swapbuffer(): + dut = SwapBuffer(Rgb666Layout, 512) + sim = Simulator(dut) + sim.add_clock(1e-6) + + async def testbench(ctx): + init_color = {"red": 0, "green": 0, "blue": 0} + test_color = {"red": 8, "green": 8, "blue": 8} + ctx.set(dut.selector, 0) + ctx.set(dut.write_port.addr, 1) + ctx.set(dut.read_port.addr, 1) + ctx.set(dut.write_port.data, test_color) + await ctx.tick() + # assert that the read port addr 1 = 0 + assert ctx.get(dut.read_port.data) == init_color + # swap buffer + ctx.set(dut.selector, 1) + await ctx.tick().repeat( + 2 + ) # takes two clocks after switching selector to output data. + assert ctx.get(dut.read_port.data) == test_color + + # TODO: add more assertions/verification + sim.add_testbench(testbench) + with sim.write_vcd("output.vcd"): + sim.run_until(1e-6 * 1000) + def test_stringdriver(): # the string driver test must diff --git a/src/groovylight/tests/test_swapbuffer.py b/src/groovylight/tests/test_swapbuffer.py deleted file mode 100644 index e312ba9..0000000 --- a/src/groovylight/tests/test_swapbuffer.py +++ /dev/null @@ -1,31 +0,0 @@ -from amaranth.sim import Simulator - -from ..hub75 import Hub75StringDriver, Rgb666Layout, SwapBuffer - - -def test_swapbuffer(): - dut = SwapBuffer(Rgb666Layout, 512) - sim = Simulator(dut) - sim.add_clock(1e-6) - - async def testbench(ctx): - init_color = {"red": 0, "green": 0, "blue": 0} - test_color = {"red": 8, "green": 8, "blue": 8} - ctx.set(dut.selector, 0) - ctx.set(dut.write_port.addr, 1) - ctx.set(dut.read_port.addr, 1) - ctx.set(dut.write_port.data, test_color) - await ctx.tick() - # assert that the read port addr 1 = 0 - assert ctx.get(dut.read_port.data) == init_color - # swap buffer - ctx.set(dut.selector, 1) - await ctx.tick().repeat( - 2 - ) # takes two clocks after switching selector to output data. - assert ctx.get(dut.read_port.data) == test_color - - # TODO: add more assertions/verification - sim.add_testbench(testbench) - with sim.write_vcd("output.vcd"): - sim.run_until(1e-6 * 1000)